mi17050592.pdf

Academic Editor: Indu Sharma Received: 7 April 2026 Revised: 30 April 2026 Accepted: 11 May 2026 Published: 12 May 2026 Copyright: © 2026 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access …

Academic Editor: Indu Sharma

Received: 7 April 2026

Revised: 30 April 2026

Accepted: 11 May 2026

Published: 12 May 2026

Licensee MDPI, Basel, Switzerland.

This article is an open access article

distributed under the terms and

conditions of the Creative Commons

Attribution (CC BY) license.

Article

Comparative Evaluation of Optical Alignment Algorithms for

Integrated Probe Cards in Photonic Wafer Testing

Mehdi Bejani

1,2,

* , Alessia Galli

, Riccardo Vettori

, Marco Mauri

and Stefano Mariani

Department of Civil and Environmental Engineering, Politecnico di Milano, 20133 Milano, Italy;

stefano.mariani@polimi.it

Technoprobe, 23870 Cernusco Lombardone, Italy; alessia.galli@technoprobe.com (A.G.);

riccardo.vettori@technoprobe.com (R.V.); marco.mauri@technoprobe.com (M.M.)

* Correspondence: mehdi.bejani@polimi.it

Abstract

Wafer-level testing of Photonic Integrated Circuits (PICs) represents a critical throughput

bottleneck in silicon photonics manufacturing, particularly as co-packaged optics demand

testing of thousands of optical I/O per wafer. This work introduces optimized alignment

algorithms for the Technoprobe Eclipse Dynamic probe card system, which integrates

electrical probes and a piezoelectrically actuated ﬁber array unit within a single probe head,

eliminating external positioning equipment. We systematically evaluate seven alignment

algorithms: Reference Coarse Scan, Reference Coarse+Fine Scan, Cross Scan, Local and

Global Bayesian Optimization, Variable and Fixed Gradient Ascent. The evaluation is

made across 72 simulated test cases derived from eight experimental datasets through

systematic spatial windowing, combined with experimental validation. Performance is

assessed under four operating regimes—high-speed (HS) and low-speed (LS) operation,

each with or without hysteresis compensation (H/NH). Experimental validation across

eight die positions conﬁrms 100% success rate for both Local Bayesian (98.24% accuracy

in 99.87 arbitrary units (a.u.)) and Fixed Gradient (99.18% accuracy in 154.01 a.u.) base-

line algorithms. Comprehensive simulation results with improved algorithms across all

four scenarios reveal distinct performance characteristics. Fixed Gradient achieves the

highest reliability (95.8%) with 99.4% average accuracy across all operating conditions.

Variable Gradient provides the fastest alignment (1.18 a.u. in HS-NH) with 90.3% reliability.

Local Bayesian demonstrates 94.4% reliability with intermediate performance. Global

Bayesian Optimization achieves the best sample efﬁciency (average 24 steps) but exhibits

scenario-dependent reliability ranging from 88.9% (HS-H, LS-H) to 93.1% (LS-NH). For

the ideal production scenario, high speed with effective hysteresis compensation (HS-NH),

Fixed Gradient emerges as the optimal choice, delivering 95.8% reliability with 1.44 a.u.

alignment time, resulting in the best success rate while being nearly as fast as the fastest

method. Variable Gradient achieves the absolute fastest alignment (1.18 a.u.) but with

5.5% lower reliability (90.3%), making it suitable only for applications tolerating higher

failure rates. Under realistic production conditions with uncompensated hysteresis (HS-H),

Fixed Gradient maintains its advantage (95.8% reliability, 3.32 a.u.), while Global Bayesian

degrades signiﬁcantly (88.9% reliability, 4.29 a.u.). Statistical analysis using data proﬁles

validates these methods for high-volume PIC manufacturing, with the Eclipse Dynamic

system demonstrating per-die optical alignments in sub-second timescales using open-loop

control hardware.

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Keywords: Photonic Integrated Circuits; wafer-level testing; probe card; optical alignment;

piezoelectric actuation; Bayesian optimization; hysteresis compensation

1. Introduction

Wafer-level testing of photonic integrated circuits (PICs) has emerged as a critical

bottleneck in the silicon photonics manufacturing ﬂow [

]. The convergence of opti-

cal and electronic components in PICs has revolutionized high-speed data transmission,

telecommunications, and sensing applications [

]. As PIC complexity grows exponentially,

driven by demands from data centers and 5G networks, wafer-level testing has become

increasingly critical to ensure device functionality and yield before expensive packaging

processes [2].

Unlike standard electronic ICs, PICs require simultaneous electrical and optical char-

acterization, presenting unique challenges for test equipment design. A fundamental

bottleneck in PIC wafer probing is achieving precise optical coupling between optical

ﬁbers and on-chip waveguides, which demands alignment tolerances typically in the range

of 100 nm or better across six degrees of freedom [

]. Traditionally, these alignments

have been performed using external optical positioning systems, such as hexapods and

piezoelectric actuators mounted on prober peripheries, or by slow automated routines.

While functional in lab settings, these external setups signiﬁcantly increase equipment cost,

footprint, and setup complexity, resulting in substantial test time per device [

]. With test-

ing already accounting for roughly 30% of the total manufacturing cost of a PIC device [

these external systems severely limit throughput and make parallel testing of multiple

devices challenging. This time and cost pressure is only growing as PIC volumes increase

and diverse optical I/O designs (grating couplers, edge couplers, etc.) proliferate.

The industry moving toward co-packaged optics (CPO) in high-performance comput-

ing and data centers further ampliﬁes the challenge, as wafer-level optical testing must scale

to meet the throughput demands of potentially thousands of optical I/O per wafer [

]. In

CPO-enabled photonic engines, PIC dies with dramatically higher port counts need to be

tested rapidly to avoid becoming a production bottleneck [3].

Recent advances have fundamentally changed the architecture of PIC wafer test equip-

ment. On one front, there is a push toward integrated probe head solutions that combine

optical and electrical probing in a single apparatus, eliminating the need for separate

bulky aligners. One such design philosophy relies on passive, alignment-insensitive optical

coupling: the on-card optics are engineered so that the positional tolerances of the prober

chuck alone provide adequate coupling, effectively removing per-die active alignment

overhead and pushing throughput toward the electrical-probing limit [4–6].

Our work is based on the Technoprobe Eclipse Dynamic probe system, an alternative

approach which co-integrates a ﬁber array unit (FAU) and piezoelectric micro-positioners

directly into the probe card [

]. The FAU is mounted on a ﬂexure mechanism and actuated

by three piezoelectric elements operating over a voltage range of 0–120 V, providing a

displacement range of 15

m alongside necessary tilt compensation. This enables

high-precision optical alignment through automated routines without the need for external

positioning equipment. Rather than relying on cumbersome, large, and slow external tools,

this design integrates the active alignment capability directly into a compact, dynamic probe

head, drastically reducing move-and-align times between dies. Integration of intelligent

control and monitoring frameworks [

] further enhances the capability of the system for

high-volume production environments. As a result, the typical active alignment time

(which once took on the order of tens of seconds per die) can be signiﬁcantly reduced [

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This is a necessary evolution for high-volume scenarios: an integrated optical probe card

can save precious seconds per die in alignment, which compounded over hundreds of dies

yields substantial throughput gains [6,10,11].

Equally important, integrating the optical aligners into the probe hardware enables

parallel multi-channel testing. For instance, the Eclipse Dynamic (and similar systems)

can couple many ﬁber channels at once, leveraging parallel optical tests to further boost

throughput. Probe-card-based architectures that co-integrate optical and electrical inter-

faces are already enabling this parallelism [

], and recent fully automated wafer-level

systems demonstrate the viability of high-throughput multi-site electro-optical characteri-

zation [10].

Another key aspect of our solution is its cost-effective control strategy. High-

performance aligners often employ closed-loop feedback (using interferometric sensors

or strain gauges) to achieve nanometric precision and to counteract piezo hysteresis and

drift. Piezoelectric actuators inherently exhibit this hysteresis behavior, where displacement

depends not only on the applied voltage but also on the voltage history [

]. Because this

non-linearity is particularly pronounced at higher voltages, it can signiﬁcantly impact

alignment accuracy and speed. However, implementing closed-loop control to mitigate this

in a dense multi-ﬁber probe head would add considerable complexity and cost. Instead,

the Eclipse Dynamic system exploits advanced open-loop control with algorithmic com-

pensation for these actuator nonlinearities. Furthermore, because each measurement point

requires time for actuator movement and signal settling, the choice of alignment algorithm

and operating speed regime plays a crucial role in determining overall testing throughput.

However, modern modeling techniques for piezoelectric actuators have made it feasi-

ble to achieve accuracies of a few nanometers without physical feedback sensors. Hysteresis

operators like the Preisach and Prandtl–Ishlinskii (P-I) model can be mathematically in-

verted for feedforward linearization of piezo stages [

]. Recent research has improved

upon these classical models to address rate-dependent and asymmetric hysteresis, using

modiﬁed P-I operators or even data-driven approaches (e.g., sparse and machine-learning-

based hysteresis models) for greater accuracy [

]. By leveraging such techniques, our

piezo actuators in the probe head are software-linearized, enabling repeatable sub-micron

alignments in open-loop. This avoids the need for embedded nano-position encoders

on each axis, thereby simplifying the probe hardware and enhancing robustness in a

production environment.

In this work, we present a comprehensive study of alignment optimization tech-

niques. We evaluate seven different alignment algorithms through both experimental

measurements and simulated data generated from experimental scans. Each algorithm was

evaluated across eight distinct on-wafer die locations (spanning multiple reticle positions)

directly on the Eclipse Dynamic hardware. Our analysis considers both high-speed (HS)

and low-speed (LS) operating regimes, as well as the impact of piezoelectric hysteresis on

alignment performance. Following best practices for algorithm comparison [

], we employ

data proﬁle analysis rather than simple averaging to account for the non-normal distribu-

tion of convergence steps, particularly as the number of optimization problems increases.

The key contributions of this work can thus be listed as:

•

Comprehensive experimental characterization of seven alignment algorithms on eight

real wafer-level PIC coupling scenarios;

•

Simulation framework for generating synthetic alignment scenarios with controllable

hysteresis effects;

• Statistical analysis using data proﬁles for rigorous algorithm comparison;

•

Comparative performance evaluation across high-speed and low-speed operating

conditions;

https://doi.org/10.3390/mi17050592