IPC-SM-782A-表面贴装焊盘图形设计标准.pdf.pdf - 第45页

mm thickness and a low proﬁle 0.04 mm ﬁnished thick- ness. Although pattern screen printing is available, photo- imaged soldermask is recommended for surface mount applications. The photo process provides a precise patte…

3.7.2 Soldermask Issues Rework of Surface Mount

Assemblies due to soldermask related defects is cited as a

major cause of problems by assembly people. Following

are two classes of assembly problems caused by improp-

erly applied soldermask: 1) soldermask on the component

mounting lands; 2) insufficient soldermask coverage of

unrelated circuit features in close proximity to the compo-

nent mounting land.

Regarding soldermask on the lands and assuming that the

solderability requirements of the component leads and

board mounting lands have been met, the solder paste com-

position, viscosity, and aging are within limits, and the

thermal proﬁle of the reﬂow oven is correct, the only other

variable which could be detrimental to good solder joint

integrity is soldermask material on the lands. If there is any

soldermask (even if invisible to the naked eye) on the lands

during reﬂow, solder joint integrity can be lost through

improper surface wetting.

The second class of assembly defects is created when there

is insufficient soldermask coverage of circuitry in close

proximity to the component mounting land leading to sol-

der shorts or bridging. The majority of SMT designs incor-

porate very small geometries of 0.15–0.2 mm [0.006–

0.008 in] conductors and spacing on the outer layers of the

printed board. Designing a soldermask to cover a 0.15 mm

[0.006 in] conductor and only half of the 0.15 mm [0.006

in] space between the conductor and the land is easy

enough to accomplish during design. However, photo

imaged soldermask will overcome most of the above issues

(see Section 3.7.4).

Close examination of solder bridging on Printed Board

Assemblies will reveal that most of the bridging actually

occurs between the component leads above the surface of

the PB, and not between the lands on the board. Even if a

soldermask has sufficient resolution and registration to pro-

vide a solder dam between lands, it still may not prevent

bridging between the leads. Soldermask should not, and

can not, be expected to compensate for deﬁciencies in the

soldering process if the assembly uses Fine Pitch compo-

nents.

3.7.3 Solder Mask Clearances A soldermask may be

used to isolate the land pattern from other conductive fea-

tures on the board such as vias, lands or conductors. Where

no conductors run between lands, a simple gang mask can

be used as shown in Figure 3–33. Tolerance requirements

for this design can generally be met by a screen printed

soldermask. A 0.38 mm [0.015 in] spacing could be accept-

able. Any class of solder mask per IPC-SM-840 could be

applied. The most commonly chosen solder mask would be

a Class 3 mask because of its higher temperature character-

istics. Due to the close proximity of the solder mask to the

land pattern, care must be taken in choosing a mask that

has low ﬂow and low solvent-bleed characteristics to avoid

land pattern contamination.

For land pattern designs with routed conductors between

lands (Figure 3–34) the tolerance requirement would

require a photo-imageable soldermask. This is necessary

because of the tight tolerance needed to cover the conduc-

tors without encroaching on the land area. A 0.08 to 0.125

mm [0.003 to 0.005 in] clearance is required with this type

of design.

3.7.4 Soldermask Types Solder mask coatings are avail-

able in two forms, liquid and dry ﬁlm. The polymer mask

material is applied using several process methods and are

furnished in varying thicknesses. As an example, liquid

materials will have a ﬁnished thickness of 0.02 to 0.025

mm while the dry ﬁlm products are supplied for 0.08–0.10

IPC-782-3-33

Figure 3–33 Gang solder mask window

Solder Mask

Land

Gang

▼

IPC-782-3-34

Figure 3–34 Pocket solder mask windows

Land

Conductor

▼

Pocket

IPC-SM-782A December 1999

mm thickness and a low proﬁle 0.04 mm ﬁnished thick-

ness. Although pattern screen printing is available, photo-

imaged soldermask is recommended for surface mount

applications.

The photo process provides a precise pattern image and

when properly developed eliminates mask residue from

land pattern surfaces. The mask thickness may not be a

factor on most surface mount assemblies but when ﬁne

pitch (0.63 mm or less) devices are mounted on the printed

boards, the lower proﬁle soldermask will provide better

solder printing characteristics.

4.0 QUALITY AND RELIABILITY VALIDATION

4.1 Validation Techniques

The variety of component

tolerances, and the possibility that tolerances may vary on

interconnection products, users are encouraged to establish

validation of the land pattern and component geometry. In

addition, components should be checked for their maxi-

mum operating temperature limits. Figure 4–1 shows a

general graph of the upper and lower limits of various

components.

Validations of parts and circuits may be accomplished

through the use of standard test patterns. These patterns

may be used not only to evaluate a particular part to a land

pattern, but may also be used to evaluate a particular inter-

connection product that must go through the various pro-

cesses being used in assembling surface mounted parts.

4.1.1 Test Patterns—Process Evaluations The follow-

ing test patterns have been developed as standards that may

be used for the evaluation of standard board materials, with

a variety of standard parts. IPC-A-49 artwork is available

for these tests. The land patterns represent land pattern

designs from the original IPC-SM-782.

The test specimen contains conductors and plated through

holes and parts connected in a single daisy chain. One end

of the daisy chain is connected to a common ground while

the other end of the chain is connected to land patterns,

then to a plated through hole in which a wire may be sol-

dered for test purposes.

IPC-782-4-1

Figure 4–1 Component temperature limits

Maximum Operating Limits for Components

125

120

0°C

–40–40

–10

–55

Ceramic ICs

Plastic ICs

Capacitors

Resistors

▼ ▼

▼

December 1999 IPC-SM-782A

Circuits that are shown in Figures 4–2 and 4–3 contain the

various components listed:

Test Vehicle

Primary (Top) Side

__ SITE #1

(2) 44 I/O PLCC-J

__ SITE #2

(2) 16 I/O DIP-I

__ SITE #3

(8) RC1206

(8) SOT-23

__ SITE #4

(1) 68 I/O CLCC-J

__ SITE #5

(68) I/O PLCC-J

__ SITE #6

(8) MELF 1/4W

(8) CC1825

__ SITE #8

(2) 24 I/O SOIC-L

Secondary (Bottom) Side

__ SITE #1

Empty

__ SITE #2

Empty

__ SITE #3

(8) RC1206

(8) SOT-23

__ SITE #4

Empty

__ SITE #5

Empty

__ SITE #6

(8) MELF 1/4W

(8) CC1825

__ SITE #8

Empty

Another test specimen is used for the testing of printed

board structures that are intended to provide P&I structures

used primarily for the mounting of leadless chip carriers.

This test board is described in surface mount land pattern

round robin artwork (IPC-A-48). The board is a 12-layer

multilayer board which contains 38 positions for mounting

leadless chip carriers used by an Air Force Mantech Pro-

gram to evaluate printed board and substrate materials. The

test boards produced from this artwork may contain metal

cores, or other planes that control the coefficient of thermal

expansion of the P&I structure.

The following are some examples of the type of materials

that may be used as the constraining core.

• Nonorganic materials (alumina)

• Porcelainized clad Invar materials

• Printed boards bonded to low-expansion support

(metal or nonmetal)

• Compliant layer constructions

• Metal core boards

4.2 Test Patterns—In-Process Validator Test patterns

to validate in-process conditions are encourage to be incor-

porated into the panel of a printed board assembly. These

designed-in land patterns provide special features for auto-

matic optical inspection and visual inspection.

The land patterns shown in section 8–13 are designed to

provide a clear view of the soldering characteristic such

that land geometry is visible, and solder joint evaluation

can be achieved. The same in-process validator are used to

check the registration of solder paste prior to reﬂow solder-

ing.

Figures 4–4 through 4–11 are illustrations from J-STD-001

that provide the key variables for meeting soldering

requirements that are necessary for various surface mount

parts. Land pattern samples provided around the periphery

of a panel, should be designed to provide clear visibility of

the solder joints shown in these ﬁgures.

4.3 Stress Testing Stress testing usually consists of tem-

perature cycling of the printed board assembly that has

been surface mounted through various extremes. The tem-

perature cycling of the assembly or a coupon may be a

standard MIL- STD-202 test method which cycles the

board from –65°C to 125°C.

Alternate temperature cycles are also available. A tempera-

ture cycle test of 400 consecutive cycles to 1000 cycles has

been identiﬁed for some assemblies. In these examples, the

ramp time from high to low temperature is 30 minutes, and

the time at the extreme is also 30 minutes. Figure 4–12

shows an example of the excursion rate of the various con-

ditions of temperature cycling.

During the cycling processes, daisy chained plated-through

holes and daisy chained solder joints, are measured during

the initial phase as to their resistance, and then monitored

for increased resistance during the thermal cycling.

Increased resistance of 30 microohms in most instances

constitutes a failure of the either the plated-through hole, or

the solder joint.

IPC-SM-782A December 1999