IPC-SM-782A-表面贴装焊盘图形设计标准.pdf.pdf - 第6页

Table of Contents 1.0 SCOPE ...................................................................... 1 1.1 Purpose ................................................................. 1 1.2 Performance Classiﬁcation .........…

Riesenbeck, J., Lytton Inc.

Rietdorf, B.C., Hughes Defense

Communications

Rudy, D., Lucent Technologies Inc.

Rumps, D.W., Lucent Technologies

Inc.

Russell, R., Texas Instruments Inc.

Seltzer, M.L., Hughes Delco Systems

Operations

Siegel, E.S., Pace Inc.

Skelly, H., Boeing Defense & Space

Group

Smith, E., Lucent Technologies Inc.

Socolowski, N., Alpha Metals Inc.

Solberg, V., Tessera Inc.

Stepp, L., Whittaker Electronic

Systems

Theiler, G.P., Fluke Corporation

Theroux, G., Honeywell Inc.

Thompson, R.T., Loctite Corporation

Thrasher, H.M., Shipley Co.

Torres, S., Corlund Electronics Corp.

Treutler, L.E., Fachverband

Elektronik Design e.V.

Turbini, L.J., Georgia Institute of

Technology

Vanech, R., Northrop Grumman

Norden Systems

Vaught, J., Hughes Aircraft Co.

Virmani, N., NASA/Goddard Space

Flight Center

Vollmar, E.L, Methode Electronics

Inc.

Weiner, E.M., Weiner & Associates

Inc.

Weiner, M., Tadiran Telecom Group

White, T.M., Boeing Defense &

Space Group

Williams, J.J., Smiths Industries

Wingate, P., Amkor Electronics Inc.

Winslow, H., SCI Systems Inc.

Wood, M., The Surface Mount

Technology Centre Inc.

Woodhouse, G.P., Micron Custom

Mfg. Services Inc.

Wooldridge, J.R., Rockwell

International

Wu, F.B., Hughes Aircraft Co.

Special Note of Appreciation

A special note of appreciation goes to

the following principle members of

the committee who led the effort to

make this document possible.

John Biancini, Advanced Flex

Gary Ferrari, IPC

Cynthia Jonas, Pitney Bowes

Vern Solberg, Tessera Inc.

Vivian Vosburg, Pac-El

Cover art by:

IPC Designers Council

William Burt

Custom Photo and Design, Inc.

December 1999 IPC-SM-782A

iii

Table of Contents

1.0 SCOPE...................................................................... 1

1.1 Purpose................................................................. 1

1.2 Performance Classiﬁcation.................................. 1

1.3 Assembly Types................................................... 2

1.4 Presentation.......................................................... 2

1.5 Proﬁle Tolerances................................................. 2

1.6 Land Pattern Determination ............................... 2

2.0 APPLICABLE DOCUMENTS................................... 4

2.1 IPC ...................................................................... 4

2.2 Electronic Industries Association ....................... 4

2.3 Joint Industry Standards (IPC)............................ 5

2.4 American Society of Mechanical Engineers....... 5

3.0 DESIGN REQUIREMENTS ..................................... 5

3.1 Terms and Deﬁnitions.......................................... 5

3.2 Component Acronyms ......................................... 7

3.3 Dimensioning Systems ........................................ 7

3.4 Design for Producibility.................................... 17

3.5 Environmental Constraints ............................... 18

3.6 Design Rules...................................................... 20

3.7 Outer Layer Finishes ........................................ 34

4.0 QUALITY AND RELIABILITY VALIDATION ....... 37

4.1 Validation Techniques........................................ 37

4.2 Test Patterns—In-Process Validator.................. 38

4.3 Stress Testing ..................................................... 38

5.0 TESTABILITY ........................................................ 45

5.1

Testing Considerations ..................................... 45

5.2

Nodal Access...................................................... 45

5.3

Full Nodal Access.............................................. 46

5.4

Limited Nodal Access........................................ 47

5.5

No Nodal Access ............................................... 47

5.6

Clam Shell Fixtures Impact............................... 48

5.7

Printed Board Test Characteristics ................... 48

6.0 PACKAGING AND INTERCONNECTING

STRUCTURE TYPES

............................................. 48

6.1

General Considerations...................................... 49

6.2

Organic-Base Material P&IS............................. 50

6.3

Non-Organic Base Materials............................. 50

6.4

Supporting-Plane P&I Structures...................... 50

6.5

Constraining Core P&I Structures .................... 52

7.0 ASSEMBLY CONSIDERATIONS FOR

SURFACE MOUNT TECHNOLOGY (SMT)

........... 53

7.1

SMT Assembly Process Sequence .................... 53

7.2 Substrate Preparation Adhesive,

Solder Paste ...................................................... 53

7.3 Component Placement....................................... 53

7.4 Soldering............................................................ 56

7.5 Cleaning ............................................................. 57

7.6

Repair/Rework ................................................... 57

8.0 DISCRETE COMPONENTS

8.1 Chip Resistors

8.2 Chip Capacitors

8.3 Inductors

8.4 Tantalum Capacitors

8.5 Metal Electrode Face (MELF) Components

8.6 Small Outline Transistor (SOT) 23

8.7 Small Outline Transistor (SOT) 89

8.8 Small Outline Diode (SOD) 123

8.9 Small Outline Transistor (SOT) 143

8.10 Small Outline Transistor (SOT) 223

8.11 Modiﬁed Through-Hole Component (TO) 252

9.0 COMPONENTS WITH GULLWING LEADS ON

TWO SIDES

9.1 Small Outline Integrated Circuits (SOIC)

9.2 Small Outline Integrated Circuits (SSOIC)

9.3 Small Outline Package Integrated Circuit

(SOPIC)

9.4 Thin Small Outline Package

9.5 Ceramic Flat Pack (CFP)

10.0 COMPONENTS WITH J LEADS ON TWO SIDES

10.1 Small Outline Integrated Circuits with J Leads

(SOJ)–7.63 mm [0.300] Body Size

10.2 Small Outline Integrated Circuits with J Leads

(SOJ)–8.88 mm [0.350] Body Size

10.3 Small Outline Integrated Circuits with J Leads

(SOJ)–10.12 mm [0.400] Body Size

10.4 Small Outline Integrated Circuits with J Leads

(SOJ)–11.38 mm [0.450] Body Size

11.0 COMPONENTS WITH GULLWING LEADS ON

FOUR SIDES

11.1 Plastic Quad Flat Pack (PQFP)

11.2 Shink Quad Flat Pack (SQFP), Square

11.3 Shrink Quad Flat Pack (SQFP), Rectangular

11.4 Ceramic Quad Flat Pack (CQFP)

12.0 COMPONENTS WITH J LEADS ON FOUR SIDES

12.1 Plastic Leaded Chip Carrier (PLCC), Square

12.2 Plastic Leaded Chip Carrier (PLCC), Rectangular

12.3 Leadless Ceramic Chip Carrier (LCC)

13.0 MODIFIED DUAL-IN-LINE PIN (DIP)

COMPONENTS

December 1999 IPC-SM-782A

13.1 DIP

14.0 COMPONENTS WITH BALL GRID ARRAY

CONTACTS

14.1 Plastic Ball Grid Array

14.2 1.27 mm Pitch Rectangular PBGA JEDEC

MS-028

Figures

Figure 1–1 Electrical assembly types.................................. 3

Figure 3–1 Examples of typical package styles and

package descriptive designators....................... 9

Figure 3–2 Lead-form (or terminal-shape) examples........ 10

Figure 3–3 Proﬁle tolerancing examples ........................... 11

Figure 3–4 Example of C1206 capacitor dimensioning

for optimum solder ﬁllet conditions ................. 12

Figure 3–5 Proﬁle dimensioning of a gullwing

leaded SOIC.................................................... 13

Figure 3–6 Pitch for multiple-leaded components............. 15

Figure 3–7 Simpliﬁed electronic development

organization..................................................... 20

Figure 3–8 Recommended minimum land-to-land

clearances....................................................... 21

Figure 3–9 Component orientation for wave solder

applications...................................................... 21

Figure 3–10 Alignment of similar components.................... 22

Figure 3–11 Local/global ﬁducials....................................... 23

Figure 3–12 Panel/global ﬁducials....................................... 23

Figure 3–13 Fiducial types for vision systems .................... 24

Figure 3–14 Fiducial clearance requirements ..................... 24

Figure 3–15 Fiducial locations on a printed circuit board ... 25

Figure 3–16 Packaging and geometries.............................. 25

Figure 3–17 Surface mount conductor widths/

clearances vs. routing grids ............................ 26

Figure 3–18 Section view of multilayer board with

vias on 1.0 mm [0.040 in] centers .................. 26

Figure 3–19 Narrowed conductor........................................ 27

Figure 3–20 Conductor routing............................................ 27

Figure 3–21 Surface routing geometries............................. 28

Figure 3–22 Conductor routing capability test pattern ........ 28

Figure 3–23 Routing channels under SOIC land

pattern with 28 pins......................................... 29

Figure 3–24 Land pattern to via relationships..................... 29

Figure 3–25 Examples of via positioning concepts............. 30

Figure 3–26 Vias under components .................................. 30

Figure 3–27 Conductor characteristics................................ 31

Figure 3–28 Examples of modiﬁed landscapes .................. 32

Figure 3–29

Typical copper glass laminate panel............... 33

Figure 3–30

Conductor clearance for V-groove scoring ..... 34

Figure 3–31

Breakaway (routed pattern)............................. 35

Figure 3–32

Routed slots .................................................... 35

Figure 3–33

Gang solder mask window.............................. 36

Figure 3–34

Pocket solder mask windows.......................... 36

Figure 4–1 Component temperature limits........................ 37

Figure 4–2 General description of process validation

contact pattern and interconnect..................... 39

Figure 4–3 Photo image of IPC-A-49 test board for

primary side..................................................... 39

Figure 4–4 Flat ribbon, ‘‘L,’’ and gullwing lead joint

description....................................................... 40

Figure 4–5 Round or ﬂattened (coined) lead joint

description....................................................... 40

Figure 4–6 ‘‘J’’ lead joint description ................................. 41

Figure 4–7 Rectangular or square end components......... 41

Figure 4–8 Cylindrical end cap terminations—joint

illustration ........................................................ 42

Figure 4–9 Bottom only terminations................................. 42

Figure 4–10 Leadless chip carriers with castellated

terminations—joint description........................ 43

Figure 4–11 Butt joint description........................................ 43

Figure 4–12 Thermal cycle excursion rate.......................... 44

Figure 5–1 Test via grid concepts ..................................... 47

Figure 5–2 General relationship between test contact

size and test probe misses ............................. 49

Figure 5–3 Test probe feature distance from

component....................................................... 50

Figure 7–1 Typical process ﬂow for underside

attachment type 2c (simple) surface mount

technology....................................................... 54

Figure 7–2 Typical process ﬂow for full surface

mount type 1b and 2b surface mount

technology....................................................... 54

Figure 7–3 Typical process ﬂow for mixed technology

type 2c (complex) surface mount

technology....................................................... 55

Figure 7–4 In-line placement equipment........................... 55

Figure 7–5 Simultaneous placement equipment............... 55

Figure 7–6 Sequential placement equipment.................... 56

Figure 7–7 Sequential/Simultaneous placement

equipment........................................................ 56

Tables

Table 3–1 Terminal Position Preﬁxes.................................... 8

Table 3–2 Package-Outline-Style Codes.............................. 8

Table 3–3 Lead-Form (or Terminal-Shape) Suffixes........... 11

Table 3–4 Tolerance Analysis Elements for Chip Devices

Table 3–5 RLP Numbers..................................................... 17

Table 3–6 Worst-Case Environments and Appropriate

Equivalent Accelerated Testing .......................... 19

Table 3–7 Component Stand Off ........................................ 23

Table 3–8 Typical Values to Be Added or Subtracted to

Nominal Production to Achieve Desired

Nominal Conductor Width.................................. 31

Table 3–9 Conductor Width Tolerances.............................. 32

Table 6–1 Packaging and Interconnecting Structure

Comparison........................................................ 51

Table 6–2

P & I Structure Selection Considerations .......... 52

Table 6–3

P & I Structure Material Properties.................... 52

IPC-SM-782A December 1999