IPC-SM-782A-表面贴装焊盘图形设计标准.pdf.pdf - 第77页

5.0 LAND PATTERN DIMENSIONS Figure 3 provides the land pattern dimensions for chip capaci- tors. These numbers represent industry consensus on the best dimensions based on empirical knowledge of fabricated land patterns.…

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4.0 COMPONENT DIMENSIONS
Figure 2 provides the component dimensions for chip capacitors.
Component
Identifier
(mm) [in]
LSWTH
min max min max min max min max max
1005 [0402] 0.90 1.10 0.30 0.65 0.40 0.60 0.10 0.30 0.60
1310 [0504] 1.02 1.32 0.26 0.72 0.77 1.27 0.13 0.38 1.02
1608 [0603] 1.45 1.75 0.45 0.97 0.65 0.95 0.20 0.50 0.85
2012 [0805] 1.80 2.20 0.30 1.11 1.05 1.45 0.25 0.75 1.10
3216 [1206] 3.00 3.40 1.50 2.31 1.40 1.80 0.25 0.75 1.35
3225 [1210] 3.00 3.40 1.50 2.31 2.30 2.70 0.25 0.75 1.35
4532 [1812] 4.20 4.80 2.30 3.46 3.00 3.40 0.25 0.95 1.35
4564 [1825] 4.20 4.80 2.30 3.46 6.00 6.80 0.25 0.95 1.10
Figure 2 Chip capacitor component dimensions
L
S
T
W
H
IPC-782-8-2-2
IPC-SM-782
Subject
Chip Capacitors
Date
5/96
Section
8.2
Revision
A
Page2of4
5.0 LAND PATTERN DIMENSIONS
Figure 3 provides the land pattern dimensions for chip capaci-
tors. These numbers represent industry consensus on the
best dimensions based on empirical knowledge of fabricated
land patterns.
In the table, the dimensions shown are at maximum material
condition (MMC). The least material condition (LMC) should
not exceed the fabrication (F) allowance shown on page 4.
The LMC and the MMC provide the limits for each dimension.
The dotted line in Figure 3 shows the grid placement court-
yard which is the area required to place land patterns and
their respective components in adjacent proximity without
interference or shorting. Numbers in the table represent the
number of grid elements (each element is 0.5 by 0.5 mm) in
accordance with the international grid detailed in IEC publica-
tion 97.
RLP No.
Component Identifier
(mm) [in] Z (mm) G (mm) X (mm)
YC
Placement Grid
(No. of Grid elements)ref ref
130A 1005 [0402] 2.20 0.40 0.70 0.90 1.30 2x6
131A 1310 [0504] 2.40 0.40 1.30 1.00 1.40 4x6
132A 1608 [0603] 2.80 0.60 1.00 1.10 1.70 4x6
133A 2012 [0805] 3.20 0.60 1.50 1.30 1.90 4x8
134A 3216 [1206] 4.40 1.20 1.80 1.60 2.80 4x10
135A 3225 [1210] 4.40 1.20 2.70 1.60 2.80 6x10
136A 4532 [1812] 5.80 2.00 3.40 1.90 3.90 8x12
137A 4564 [1825] 5.80 2.00 6.80 1.90 3.90 14x12
Figure 3 Chip capacitor land pattern dimensions
▼
▼
▼
▼
▼
▼
▼
▼
▼
C
G
Z
X
Y
Grid
placement
courtyard
▼
IPC-782-8-2-3
IPC-SM-782
Subject
Chip Capacitors
Date
5/96
Section
8.2
Revision
A
Page3of4
6.0 TOLERANCE AND SOLDER JOINT ANALYSIS
Figure 4 provides an analysis of tolerance assumptions and
resultant solder joints based on the land pattern dimensions
shown in Figure 3. Tolerances for the component dimensions,
the land pattern dimensions (fabrication tolerances on the
interconnecting substrate), and the component placement
equipment accuracy are all taken into consideration.
Figure 4 provides the solder joint minimums for toe, heel, and
side fillets, as discussed in Section 3.3. The tolerances are
addressed in a statistical mode, and assume even distribution
of the tolerances for component, fabrication, and placement
accuracy.
Individual tolerances for fabrication (‘‘F’’) and component
placement equipment accuracy (‘‘P’’) are assumed to be as
given in the table. These numbers may be modified based on
user equipment capability or fabrication criteria. Component
tolerance ranges (C
L
,C
S
, and C
W
) are derived by subtracting
minimum from maximum dimensions given in Figure 2. The
user may also modify these numbers, based on experience
with their suppliers. Modification of tolerances may result in
alternate land patterns (patterns with dimensions other than
the IPC registered land pattern dimensions).
The dimensions for minimum solder fillets at the toe, heel, or
side (J
T
,J
H
,J
S
) have been determined based on industry
empirical knowledge and reliability testing. Solder joint
strength is greatly determined by solder volume. An observ-
able solder fillet is necessary for evidence of proper wetting.
Thus, the values in the table usually provide for a positive sol-
der fillet. Nevertheless, the user may increase or decrease the
minimum value based on process capability.
RLP No.
Tolerance
Assumptions (mm)
Solder Joint
Toe (mm) Heel (mm) Side (mm)
FPC
L
J
Tmin
J
Tmax
C
s
J
Hmin
J
Hmax
C
W
J
Smin
J
Smax
130A 0.10 0.10 0.20 0.53 0.65 0.60 –0.06 0.12 0.20 0.03 0.15
131A 0.10 0.10 0.30 0.52 0.69 1.00 –0.08 0.16 0.50 0.01 0.27
132A 0.10 0.10 0.30 0.51 0.68 0.65 –0.08 0.18 0.30 0.01 0.18
133A 0.10 0.10 0.40 0.49 0.70 0.95 –0.16 0.26 0.40 0.01 0.23
134A 0.10 0.10 0.40 0.49 0.70 1.40 0.14 0.56 0.40 –0.01 0.20
135A 0.10 0.10 0.40 0.49 0.70 1.40 0.14 0.56 0.40 –0.01 0.20
136A 0.10 0.10 0.60 0.49 0.80 1.10 0.15 0.73 0.40 –0.01 0.20
137A 0.10 0.10 0.60 0.49 0.80 1.10 0.15 0.73 0.80 –0.01 0.40
Figure 4 Tolerance and solder joint analysis
Wmin
Lmin
▼
▼
Zmax
▼
▼
1
/2 T
T
J
T
min
Zmax = Lmin + 2J
T
min + T
T
Where:
J
T
min = Minimum toe fillet
T
T
= Combined tolerances
at toe fillet
Smax
J
H
min
Gmin = Smax - 2J
H
min - T
H
Where:
J
H
min = Minimum heel fillet
T
H
= Combined tolerances
at heel fillet
1
/2 T
H
Xmax
Xmax = Wmin + 2J
S
min + T
S
Where:
J
S
min = Minimum side fillet
T
S
= Combined tolerances
at side fillet
▼
▼
Toe Fillet
1
/2 T
S
▼
▼
▼
Heel Fillet Side Fillet
▼
▼
▼
▼
▼
J
T
max
J
H
max
J
S
max
J
S
min
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
Gmin
▼
▼
IPC-782-8-2-4
IPC-SM-782
Subject
Chip Capacitors
Date
5/96
Section
8.2
Revision
A
Page4of4