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V alid line The VBN T est Strategy FUNCTIONAL TEST WITH JT AG Despite that almost twenty years have passed since the initial introduction of JT AG 1149 testability standard, very little, or no advances, have been made in…
OPEN SOFTWARE ENVIRONMENT
All Seica instruments are fully supported by COM libraries to allow direct integration
with external environments, such as NI TestStand or Agilent VEE, and can be
programmed by external languages or graphic tools. Similarly, the Seica test
environment can call directly and execute software objects developed within external
test engines like LabView, LabWindows CVI, etc. This architecture allows the user the
advantages of years of experience embedded in Seica’s products and the flexibility to
take advantage of other commercial products as well.
For example, allowing customers the freedom to use the most suitable test sequencer,
test language, or graphic tool.
The figure below shows one of the
instruments of the ACL card,
controlled within LabView.
The following block diagram
shows the diversity, flexibility,
and interconnection of the
software modules within the
Valid Line.
Valid line
The VBN Test Strategy
FUNCTIONAL TEST WITH JTAG
Despite that almost twenty years have passed since the initial
introduction of JTAG 1149 testability standard, very little, or no
advances, have been made in combination with functional testers.
The technology has given rise to a variety of dedicated test systems,
focused on structural fault detection of components that are
boundary scan compliant and included in JTAG cells on the unit
under test. Use of JTAG has also been extended by encapsulating
the technique into ICT or Flying Probe test systems in order to
increase the structural fault coverage. Functional test has not yet
taken advantage of this technology, and has therefore continued to
struggle with high cost of test program generation, due to the
increase of components complexity and lack of control and
observation points on UUT. Fortunately, this issue has been recently
addressed on the Valid Line, with the introduction of an innovative
test generation technique, called VBN, for Virtual Bed of Nails. With
VBN, the user is encouraged to segment the UUT into clusters of
components that offer easier test generation and can be accessed
via a combination of physical pins and virtual pins, where the latter
are pins connected to a JTAG chain. All that is required is to declare
those pins as Virtual Channels, and to describe to the system the
BSDL (boundary scan description language) for each JTAG
component and the JTAG interconnection path within the netlist of
the board. The programmer can now prepare his/her test program
“as if physical and virtual channels were the same.” Once this is
done, the tester will automatically convert the parallel test program
into the appropriate mixture of parallel and JTAG TAP vectors and
generate them as required. The test results and diagnostic results
will also be displayed to the user consistently with this cluster test
approach. VBN allows functional test to take advantage of the
presence of JTAG components on the UUT and reflect it into reduced
test generation cost, increased fault coverage and diagnostic
resolution.
ROUTING ARCHITECTURE
Routing signals from instrumentation to the UUT has always been the
bottleneck for the test system. An easy solution is, of course, to bring all
signals from instrumentation to the receiver, and then assure switching
and connections on the fixture; but at what cost! Most ATE solutions
have an internal signal bus, where instruments connect through
instrument switching cards, as well as separate switching channel cards
going to the UUT. To limit space required by the matrix relays, complex
multiplexing solutions are often used. Instead, the Valid Line uses a
more flexible 3D routing architecture that avoids multiplexing limitations,
relies on an eight lines signal bus, and yet allows simultaneous
connection of a larger number of stimuli and measurements to the UUT.
This is accomplished by the S64A module, a 3D scanner matrix card,
used to switch the internal/external ATE instrumentation to the receiver.
The card contains 32x8 groups of reed relays able to connect the eight
lines of the signal bus to any of the 32 channels going to the ATE
receiver and to the UUT. The unique architecture of the card also allows
connection to eight external channels (extended bus), available on
dedicated coaxial connectors. External instrumentation can be routed
through the card, allowing either local or global connections. In local
mode, the card creates a cluster matrix, 8x32, between the instruments
connected to the card and its 32 channels, isolated from the rest of the
system. In global mode, the instruments are also connected to the signal bus,
becoming available to every channel of the system. A combination of local and
global bus connections through multiple cards allows having a large number
of different analog stimuli to be applied and measured during the same test
scenario. These features are particularly valued when board testing legacy
replacement solutions are offered, or for STE integrators of second level test
equipment.
In the figure below, instrument A is actually
connected on a local mode to pin(s) of the first
channel card, while instrument B is connected on
global mode and available to all channels of the
system.
Seica reserves the right to change
the technical specifications without notice
Brochure Valid Line UK ver. 03 01/2011
Brochure Valid Line UK ver. 02 10/2013
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Seica reserves the right to change
the technical specifications without
notice