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SEMI M2-1103 © SEMI 1985, 2003 1 SEMI M2-1103 SPECIFICATlON FOR SILICON EPIT AXIAL WAFERS FOR DISCRETE DEVICE APPLICATIONS This specification was technically approved by th e Global Silicon Wafer Committee and is the dir…
SEMI M1-0305 © SEMI 1978, 2005 50
REVISION RECORD
NOTICE: The Revision Record is an official part of the standard. It is optional and placed at the end of the
standard. Negative votes may not be based on the Revision Record.
Cycle Ballot Section Description Committee
Approval
0305 3907 Entire
Document
This revision combines most of SEMI M1 with parts of SEMI M18 to
form a new set of specifications that includes:
Purpose, a new scope, referenced standards, ordering information
(consolidated with some of SEMI M18), requirements (assembled
from several existing sections in SEMI M1), sampling, test methods,
certification, and packing and shipping container labeling sections;
Basic polished wafer specifications (developed by the Basic Wafer
Specification TF);
The two appendices and one related information section included in
previous editions of SEMI M1; and
A new related information section on detailed discussion of test
methods, based largely on material previously in SEMI M28.
A new table of contents has been added to make it easier to locate
specific information in the standard, and the terminology section of
SEMI M1 was combined with SEMI MF1241 and issued as SEMI
M59. The EDI codes from SEMI M18 remain in that standard.
The material in all of the substandards previously included at the end of
SEMI M1 is now included in the body of the document with no change
of the technical content. In addition, polished wafers and substrates
have been assigned category numbers based on the previous
substandard designation number. In some cases there are two
categories, based on differences in the edge rounding template used.
All of the specification requirements previously in the substandards
have been moved to tables as follows:
Substandard Nominal Diameter Located in Table Wafer Category(s)
SEMI M1.1 2 inch 4 1.1
SEMI M1.2 3 inch 4 1.2
SEMI M1.5 100 mm 5 1.5
SEMI M1.6 100 mm 5 1.6
SEMI M1.7 125 mm 5 1.7
SEMI M1.8 150 mm 6 1.8.1 and 1.8.2
SEMI M1.9 200 mm 9 1.9.1 and 1.9.2
SEMI M1.10 200 mm 8 1.10.1 and 1.10.2
SEMI M1.11 100 mm 7 1.11
SEMI M1.12 125 mm 7 1.12
SEMI M1.13 150 mm 8 1.13.1 and 1.13.2
SEMI M1.15 300 mm 9 1.15
Additional material related to 300 mm wafers is given elsewhere in
SEMI M1, most notably in ¶6.5.1.4, which describes the wafer marking
requirements. Also it should be noted that (1) the information on
surface orientation, for which the substandards allowed any of a
number of options, has been moved to Item 2-1.8 of Table 1, Silicon
Wafer Specification Format for Order Entry, Parts 1 and 2, and (2) the
information on orthogonal misorientation, which is the same for all
(111) silicon wafers has been moved to Item 2-1.9 of the same table.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction of
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M2-1103 © SEMI 1985, 2003 1
SEMI M2-1103
SPECIFICATlON FOR SILICON EPITAXIAL WAFERS FOR DISCRETE
DEVICE APPLICATIONS
This specification was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the North American Silicon Wafer Committee. Current edition approved by the North
American Regional Standards Committee on July 12, 2003. Initially available at www.semi.org October
2003; to be published November 2003. Originally published in 1985; previously published September 1997.
1 Purpose
1.1 This specification defines silicon epitaxial wafer
requirements for discrete semiconductor device
manufacture. It is restricted to wafers with device
feature sizes in excess of 1 µm or wafers with epi layers
thicker than 25 µm. By defining inspection procedures
and acceptance criteria, suppliers and consumers may
uniformly define product characteristics and quality
requirements.
2 Scope
2.1 This specification covers characteristics of both the
substrate (through reference to SEMI M1) and the
epitaxial layer including handling and packaging.
2.2 This specification is specifically directed to silicon
homoepitaxial deposits thicker than 25 µm on
homogeneous silicon substrates or similar epitaxial
wafers that are to be used to make discrete devices.
Specifications for silicon epitaxial wafers with greater
uniformity and more stringent surface defect criteria are
given in SEMI M11
.
2.3 The primary standardized properties set forth in
this specification relate to physical, electrical, and
surface defect parameters.
2.4 A complete purchase specification requires that
additional physical properties be specified along with
suitable test methods for their measurement. SEMI
M18 may be used for this purpose.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Referenced Standards
3.1 SEMI Standards
SEMI M1 — Specifications for Polished
Monocrystalline Silicon Wafers
SEMI M11 — Specifications for Silicon Epitaxial
Wafers for Integrated Circuit (IC) Applications
SEMI M17 — Specification for a Universal Wafer Grid
SEMI M18 — Format for Silicon Wafer Specification
Form for Order Entry
SEMI MF95 — Test Method for Thickness of Epitaxial
Layers of Silicon on Substrates of the Same Type by
Infrared Reflectance
SEMI MF110 — Test Method for Thickness of
Epitaxial or Diffused Layers in Silicon by the Angle
Lapping and Staining Technique
SEMI MF154 — Guide for Identification of Structures
and Contaminants Seen on Specular Silicon Surfaces
SEMI MF374 — Test Method for Sheet Resistance of
Silicon Epitaxial, Diffused, and Ion-Implanted Layers
Using an Inline Four-Point Probe with the Single
Configuration
SEMI MF398 — Test Method for Majority Carrier
Concentration in Semiconductors by Measurement of
Wavelength of the Plasma Resonance Minimum
SEMI MF523 — Practice for Unaided Visual
Inspection of Polished Silicon Slices
SEMI MF525 — Test Method for Measuring
Resistivity of Silicon Wafers Using a Spreading
Resistance Probe
SEMI MF672 — Test Method for Measuring
Resistivity Profiles Perpendicular to the Surface of a
Silicon Wafer Using a Spreading Resistance Probe
SEMI MF723 — Practice for Conversion between
Resistivity and Dopant Density for Boron-Doped and
Phosphorus-Doped Silicon
SEMI MF1241 — Terminology of Silicon Technology
SEMI MF1392 — Test Method for Determining Net
Carrier Density Profiles in Silicon Wafer by
Capacitance-Voltage Measurements with a Mercury
Probe
SEMI MF1393 — Test Method for Determining Net
Carrier Density in Silicon Wafers by Miller Feedback
Profiler Measurements with a Mercury Probe
SEMI MF1726 — Guide for Analysis of
Crystallographic Perfection of Silicon Wafers
SEMI M2-1103 © SEMI 1985, 2003 2
3.2 Other Standards
1
ANSI/ASQC Z1.4 — Sampling Procedures and Tables
for Inspection by Attributes
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
4 Terminology
4.1 Many terms relating to silicon technology are
defined in SEMI MF1241.
4.2 Descriptions of other epitaxial wafer defects
covered in Table 1 are given in SEMI MF154.
4.3 Other terms are defined as follows:
4.3.1 autodoping, of an epitaxial layer —
incorporation of dopant originating from the substrate
into the epitaxial layer. Also called self-doping.
NOTE 1: Sources of autodoping can be the back and front
surfaces and edges of the substrate, other substrates in the
reactor, the susceptor, or other parts of the deposition
assembly.
4.3.2 chemical vapor deposition, in semiconductor
technology — a process in which a controlled chemical
reaction produces a thin surface film.
NOTE 2: Epitaxial growth is an example of a special case of
chemical vapor deposition (CVD).
4.3.3 edge crown — the difference between the surface
elevation 1/8 inch (3.2 mm) from the edge of the wafer
and the elevation at the wafer edge.
4.3.4 effective layer thickness, of an epitaxial layer —
the depth from the front surface in which the net carrier
density is within the specified limits.
4.3.5 epi profile slope, of an epitaxial layer — the
difference between the net carrier density at 0.75 of the
layer thickness and the net carrier density at 0.25 of the
layer thickness divided by one-half the layer thickness:
t
NN
tt
5.0
slope profile epi
25.075.0
−
= (1)
where:
N = net carrier density, cm
−3
, and
t = layer thickness, µm.
4.3.6 epitaxial layer — a layer of single crystal
semiconductor material grown on a host substrate that
determines its orientation.
1 American Society for Quality Control, 611 East Wisconsin Avenue,
Milwaukee, WI 53202
4.3.7 epitaxy — The growth of a single crystal layer on
a substrate of the same material, homoepitaxy; or on a
substrate of different material with a compatible crystal
structure, heteroepitaxy.
4.3.8 flat zone, of an epitaxial layer — The depth from
the front surface to the point where the net carrier
density is 20% greater than or less than the average net
carrier density (see Section 8.3.2) of the region between
0.25 and 0.75 of the layer thickness.
4.3.9 thickness, of an epitaxial layer — The distance
from the surface of the wafer to the layer-substrate
interface.
4.3.10 transition width, of an epitaxial layer deposited
on a more heavily doped substrate of the same
conductivity type — The difference between the layer
thickness as determined by infrared reflectance (see
Section 8.3.1) and the flat zone based on the same
thickness measurement.
5 Ordering Information
5.1 Purchase orders for the epitaxial layer on substrates
furnished to this specification shall include the
following items:
5.1.1 Substrate characteristics,
5.1.2 Silicon source (if required) (see Note 3),
5.1.3 Conductivity type and doping source (see Note
3),
5.1.4 Etch removal (if required),
5.1.5 Center-point thickness and thickness tolerances,
5.1.6 Radial thickness variation range,
5.1.7 Center-point net carrier density and net carrier
density tolerances (or resistivity and resistivity
tolerances) (see Note 4),
5.1.8 Radial net carrier density (or resistivity) variation
range (see Note 4),
5.1.9 Epitaxial wafer defect limits,
5.1.10 Methods of test and measurements (see Section
8),
5.1.11 Lot acceptance procedures (see Section 7),
5.1.12 Certification (if required) (see Section 9), and
5.1.13 Packing and marking (see Section 10).
NOTE 3: The dopant, doping method, and growth method are
difficult to ascertain in the finished wafers. Verification test
procedures or certification of these characteristics shall be
agreed upon between the supplier and the purchaser (see
Section 9).