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SEMI M2-1103 © SEMI 1985, 2003 6 NOTICE: SEMI makes no warranties or representatio ns as to the suitability of th e standards set forth herein for any particular application. Th e determination of the suitability of the …

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SEMI M2-1103 © SEMI 1985, 2003 5
Table 1 Discrete Epitaxial Wafer Defect Limits
Item Characteristics Maximum Limit Test Method Notes
1 Stacking Faults 15 per cm
2
SEMI MF1726 1
2 Slip n = 36 grid elements SEMI M17 and SEMI
MF1726
1, 2, 3
3 Haze NONE SEMI MF523 Section 12.2 1, 4, 5
4 Scratches NONE SEMI MF523 Section 12.2 1, 5, 6
5 Edge Chips NONE SEMI MF523 Section 12.2 7
6 Edge Crown Projection above wafer surface not to exceed 1/3 of
epi layer thickness
To be defined 2, 8
7 Foreign Matter NONE SEMI MF523 Section 12.3 1, 4
8 Back Surface
Contamination
NONE SEMI MF 523 Section 12.4 1, 4
Epitaxial Layer Thickness Front Surface
Characteristics Dependent on
Layer Thickness
< 25 µm 25–50 µm 50–100 µm > 100 µm
9 Large Point Defects
(Density per m
2
)
700 900 1200 1500 SEMI MF523 or, with
automated surface
inspection equipment
≥ 20 µm LSE, based on
calibration of surface
scanning inspection
systems with polystyrene
latex spheres, 90% capture
rate
1, 2, 5
10 Total Localized Light
Scatterers
(Density per m
2
)
2000 2400 2700 3000 SEMI MF523 or with
automated surface
inspection equipment
≥ 0.5 µm LSE, based on
calibration of surface
scanning inspection
systems with polystyrene
latex spheres, 90% capture
rate
1, 2, 5
Notes:
1. Defect limits shall apply to quality area, which is defined as the entire wafer surface except a defined outer annulus: 2 inch and 3 inch = 2 mm;
100 mm and 125 mm = 3 mm; 150 mm and 200 mm = 4 mm and any are included in a window where there is a laser indentification mark.
2. Test method(s) to be agreed upon between supplier and purchaser.
3. For observation of gross slip, examine the epi layer under illumination conditions specified in Section 12.2 of SEMI MF523. For more
demanding applications, it may be desirable to etch the surface in accordance with SEMI MF1726 prior to the visual inspection.
4. Any adherent contaminants, such as stains, glovemarks, dirt, smudges, and solvent residues. This characteristic does not include point defects.
Any nonadherent contaminant or particulate matter easily removed by industry accepted cleaning techniques shall not constitute foreign matter or
haze.
5. In today’s technology, it may be possible to do this inspection using automated laser scanning systems; however, a standard test procedure has
yet to be developed. Application of automated inspection must be agreed upon between supplier and user.
6. The cumulative AQL for both front surface and back surface of wafer is 2.5%.
7. The cumulative AQL for both front surface and back surface of wafer is 1.0%. Maximum radial penetration, 1.0 mm; maximum single chip
peripheral length, 6.3 mm; maximum cumulative peripheral length, 6.3 mm.
8. Edge crowning may be reduced by pre-epitaxy edge rounding, or removed by post-epitaxy edge rounding.
SEMI M2-1103 © SEMI 1985, 2003 6
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant
literature respecting any materials mentioned herein. These standards are subject to change without notice.
The user’s attention is called to the possibility that compliance with this standard may require use of copyrighted
material or of an invention covered by patent rights. By publication of this standard, SEMI takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M3-0304 © SEMI 1978, 2004 1
SEMI M3-0304
SPECIFICATIONS FOR POLISHED MONOCRYSTALLINE SAPPHIRE
SUBSTRATES
This specification was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the North American Silicon Wafer Committee. Current edition approved by the North
American Regional Standards Committee on December 4, 2003. Initially available at www.semi.org
February 2004; to be published March 2004. Originally published in 1978; last published November 2003.
1 Purpose
1.1 Sapphire substrates are utilized for heteroepitaxial
growth of silicon films for certain types of device
structures. The properties of the films depend in part
on the properties of the substrate used. These
specifications are intended to provide specifications for
the criteria necessary for growth of films suitable for
device production.
2 Scope
2.1 These specifications cover requirements for five
sizes (from 2 inch to 150 mm) of monocrystalline high-
purity polished sapphire substrates. Dimensional and
crystallographic orientation characteristics are the only
standardized properties set forth herein. A purchase
specification may require that additional physical
properties be defined. Many of these properties are
listed, together with test methods suitable for
determining their magnitude. Additional information
and recommended specification levels for several of
these properties are provided in Related Information
sections.
2.2 These specifications are directed specifically to
sapphire substrates with one polished surface.
Substrates polished on both sides, or unpolished, or
with epitaxial deposits, are not covered; however,
purchasers of such substrates may find these
specifications to be a useful guide in defining their
requirements.
2.3 Appendix 1 covers dimensional requirements for
reclaimed 3 inch sapphire substrates.
2.4 For referee purposes, U.S. customary units shall be
used for substrates of 2.0 and 3.0 in. nominal diameters,
and SI (System International, commonly called metric)
units for 100 mm and larger diameter substrates.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety health practices and determine the
applicability of regulatory or other limitations prior to
use.
3 Referenced Standards
3.1 SEMI Standards
SEMI M1 — Specifications for Polished
Monocrystalline Silicon Wafers
SEMI MF26 — Test Methods for Determining the
Orientation of a Semiconductive Single Crystal
SEMI MF523 — Practice for Unaided Visual
Inspection of Polished Silicon Wafer Surfaces
SEMI MF533 — Test Method for Thickness and
Thickness Variation of Silicon Wafers
SEMI MF534 — Test Method for Bow of Silicon
Wafers
SEMI MF671 — Test Method for Measuring Flat
Length on Wafers of Silicon and Other Electronic
Materials
SEMI MF847 — Test Methods for Measuring
Crystallographic Orientation of Flats on Single Crystal
Silicon Wafers by X-Ray Techniques
SEMI MF928 — Test Methods for Edge Contour of
Circular Semiconductor Wafers and Rigid Disk
Substrates
SEMI MF1810 — Test Method for Counting
Preferentially Etched or Decorated Surface Defects in
Silicon Wafers
SEMI MF2074 — Guide for Measuring Diameter of
Silicon and Other Semiconductor Wafers
3.2 ASTM Standard
1
E 122 — Practice for Choice of Sample Size to
Estimate the Average Quality of a Lot or Process
1 Volume 14.02 of the Annual Book of ASTM Standards, ASTM
International, 100 Barr Harbor Drive, West Conshohoken, PA 19428-
2959, USA. Telephone: 610.832.9585, Fax: 610.832.9555, Website:
www.astm.org.