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SEMI M11-0704 © SEMI 1988, 2004 13 Figure 11 A Polysilicon Epitaxial Stacking Fault is a defect that covers a large a rea and is covered or surrounded by ESFs. This classification is used when the surface appe ars to be …
SEMI M11-0704 © SEMI 1988, 2004 12
Figure 10
Composite Defect of polysilicon growth and stacking faults. Magnification 500 times by Nomarksi
Interference Microscopy. Approximate SSIS image event size >>1.0 µm
5
µ
m
SEMI M11-0704 © SEMI 1988, 2004 13
Figure 11
A Polysilicon Epitaxial Stacking Fault is a defect that covers a large area and is covered or surrounded by
ESFs. This classification is used when the surface appears to be poly-crystalline rather than single crystal. It
is almost always a Large Area Defect and is caused by a large particle that may still be visible (see Buried
Particle). Magnification 1500 times using Nomarski Interference Microscopy. Approximate SSIS event size,
440 µm
5
µ
m
SEMI M11-0704 © SEMI 1988, 2004 14
4.4 Other terms are defined as follows:
4.4.1 autodoping, of an epitaxial layer —
incorporation of dopant originating from the substrate
into the epitaxial layer. Also called self-doping.
NOTE 3: Sources of autodoping can be the back and front
surfaces and edges of the substrate, other substrates in the
reactor, the susceptor, or other parts of the deposition
assembly.
4.4.2 chemical vapor deposition, in semiconductor
technology — a process in which a controlled chemical
reaction produces a thin surface film.
NOTE 4: Epitaxial growth is an example of a special case of
chemical vapor deposition (CVD).
4.4.3 edge crown — the difference between the surface
elevation 1/8 inch (3.2 mm) from the edge of the wafer
and the elevation at the wafer edge.
4.4.4 effective layer thickness, of an epitaxial layer —
the depth from the front surface in which the net carrier
density is within the specified limits.
4.4.5 epi profile slope, of an epitaxial layer — the
difference between the net carrier density at 0.75 of the
layer thickness and the net carrier density at 0.25 of the
layer thickness divided by one-half the layer thickness:
t
NN
tt
5.0
25.075.0
slopeprofileepi
−
=
m. kness,layer thic
and,
3-
cmdensity,carriernet
:where
µ
=
=
t
N
4.4.6 epitaxial layer — a layer of single crystal
semiconductor material grown on a host substrate
which determines its orientation.
4.4.7 epitaxy — the growth of a single crystal layer on
a substrate of the same material, homoepitaxy; or on a
substrate of different material with a compatible crystal
structure, heteroepitaxy.
4.4.8 flat zone, of an epitaxial layer — the depth from
the front surface to the point where the net carrier
density is 20% greater than or less than the average net
carrier density (see Section 7.3.2) of the region between
0.25 and 0.75 of the layer thickness.
4.4.9 laser light scattering event — a signal pulse that
exceeds a preset threshold, generated by the interaction
of a laser beam with a discrete scatterer at a wafer
surface as sensed by a detector.
4.4.10 thickness, of an epitaxial layer — the distance
from the surface of the wafer to the layer-substrate
interface.
4.4.11 transition width, of an epitaxial layer deposited
on a more heavily doped substrate of the same
conductivity type — the difference between the layer
thickness as determined by infrared reflectance (see
Section 7.3.1) and the flat zone based on the same
thickness measurement.
5 Ordering Information
5.1 Purchase orders for the epitaxial layer on substrates
furnished to this specification shall include the
following items:
5.1.1 Substrate Characteristics
5.1.2 Epitaxial Layer Characteristics
5.1.2.1 Silicon Source for Epitaxial Growth (if
required) (see Note 3.)
5.1.2.2 Epitaxial Layer Conductivity Type and Doping
Source (see Note 3.)
5.1.2.3 Etch Removal (if required)
5.1.2.4 Epitaxial Layer Center Point Thickness and
Thickness Tolerances
5.1.2.5 Epitaxial Layer Thickness Variation Range
5.1.2.6 Epitaxial Layer Centerpoint Net Carrier
Density and Net Carrier Density Tolerances (see Note
4.)
5.1.2.7 Epitaxial Layer Net Carrier Density Variation
Range
5.1.2.8 Epitaxial Layer Defect Limits
5.1.3 Methods of Test and Measurements (see Section
7.)
5.1.4 Lot Acceptance Procedures (see Section 8.)
5.1.5 Certification (if required) (see Section 9.)
5.1.6 Packing and Marking (see Section 10.)
NOTE 5: The dopant, doping method, and growth method are
difficult to ascertain in the finished wafers. Verification test
procedures or certification of these characteristics shall be
agreed upon between the supplier and the purchaser. (See
Section 9.)
NOTE 6: Care should be taken in converting between carrier
density and resistivity using SEMI MF723. Multiple
conversions may introduce differences in values. For
example, converting from carrier density (C
i
) to resistivity
and back to carrier density (C
f
), may result in C
i
not equaling
C
f
.