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SEMI M18-0704 © SEMI 1990, 2004 6 Figure 5 Cross-Section View of Epitaxial Wafer Showing the Pattern Shift, d . Not to scale: AM = MB and CN = ND 4.3.5 patter n step height — difference in vertical position of the d iffu…

SEMI M18-0704 © SEMI 1990, 2004 5

H 0609 — Test Methods of Crystalline Defects in

Silicon by Preferential Etch Techniques

H 0611 — Methods of Measurement of Thickness,

Taper, and Bow of Silicon Wafers

H 0612 — Testing Method of Resistivity for Single

Crystal Silicon Wafers (with Four Point Probe) [F 84]

H 0614 — Visual Inspection for Silicon Wafers with

Specular Surfaces

Z 8741 — Method of Measurement for Specular

Glossiness

3.8 Other Standard

ANSI/ASME B46.1 — Surface Texture (Surface

Roughness, Waviness, and Lay)

NOTICE: Unless otherwise indicated, all documents

cited shall be the latest published versions.

4 Terminology

4.1 The items listed in the form are referenced and

defined in various documents. A reference for most

items in Parts 2 and 3 of the form is listed in Table 1.

The entries in the table are keyed to the form by item

number. Because terms related to epitaxial wafers with

buried layer are defined in this standard and because no

standardized test methods for the buried layer

parameters exist, Table 1 does not include line items

from Part 4 of the form.

4.2 General term used in this standard:

4.2.1 required (req. or req'd) — when applied to a

parameter listed in the order form, a user-supplied value

is necessary to minimally define the material for

manufacture.

4.3 Terms related to epitaxial wafers with buried

layers:

4.3.1 buried layer — a diffused region in a substrate

that is, or is intended to be, covered with an epitaxial

layer.

4.3.2 alignment precision — pattern displacement in

first mask photolithography process.

NOTE 3: Alignment precision is specified by maximum

values of X and Y, the displacement of the center of the

pattern from a reference position defined in the wafer

specification in terms of the wafer coordinate system defined

in SEMI M20, and the maximum value of θ, the angle

between the x-axis of the pattern and the primary orientation

flat (see Figure 1).

7 The Amercan Society of Mechanical Engineers, United Engineering

Center, 345 E. 47th St., New York, NY 10017.

4.3.3 pattern distortion ratio — absolute magnitude of

the quotient of the (1) difference between the width of

the pattern on the substrate and the width of the pattern

on the top surface of the epitaxial layer and (2) the

thickness of the epitaxial layer.

Figure 2

First Mask Showing Angular

Displacement

Figure 3

Cross-Section View of Epitaxial Layer Showing the

Pattern Widths, a, at the Epi Surface, and b, at the

Layer-Substrate Interface

4.3.4 pattern shift ratio — lateral distance between the

center point of the pattern on the surface of the

substrate and the center point of the pattern on the

surface of the epitaxial layer divided by the epitaxial

layer thickness.

NOTE 4: Pattern shift ratio, d/t (see Figure 4), is specified in

terms of a nominal value, X, and a tolerance, ± Y, both of

which are dimensionless because both d and t are in µm.

Figure 4

Schematic Diagram Showing Line Width, A, of

Pattern on Substrate Wafer

SEMI M18-0704 © SEMI 1990, 2004 6

Figure 5

Cross-Section View of Epitaxial Wafer Showing the

Pattern Shift, d. Not to scale: AM = MB and CN =

4.3.5 pattern step height — difference in vertical

position of the diffused (buried layer) surface and the

original substrate surface, after removal of oxide.

NOTE 5: Pattern step height, A, is specified as a nominal

value, X, and a tolerance ± Y, both in nm. See Figure 5.

Figure 6

Cross-Sectional View of Epitaxial Substrate After

Oxide Removal but Before Deposition of the

Epitaxial Layer Showing the Pattern Step Height, A

4.4 Terms Related to Annealed Wafers

4.4.1 annealed wafer — wafer that has defects (COP)

free zone near the surface produces by high temperature

annealing.

4.4.1.1 hydrogen annealed wafer — annealed wafer

produced under hydrogen atmosphere.

4.4.1.2 argon annealed wafer — annealed wafer

produced under argon atmosphere.

4.5 Terms Related to SOI Wafers

4.5.1 SOI wafer — wafer that has a buried oxide layer

(BOX).

4.5.1.1 SIMOX wafer — SOI wafer made by oxygen

implantation and high temperature annealing

technology.

4.5.1.2 Bonded wafer — SOI wafer made by bonding

two silicon wafers with an insulating layer between

them. The insulating layer is typically grown oxide.

5 Use of the Form

5.1 Different parts of the specification form are used

for ordering different types of silicon wafers:

5.1.1 For polished wafers, complete Parts 1 and 2.

5.1.2 For epitaxial wafers, complete Parts 1, 2, and 3.

5.1.3 For epitaxial wafers with buried layer, complete

Parts 1, 2, 3, and 4.

5.1.4 For annealed wafers, complete parts 1, 2, and 5.

5.1.5 For SOI wafers, complete Parts 1, 2, and 6. If

necessary, complete Parts 3, 4, or 5.

5.2 In all cases, items listed as required must have a

value or choice indicated to minimally specify the

material.

5.3 Certain required dimensional items may be

specified as a group according to the standard values

presented in the applicable SEMI specification, or they

may be specified individually.

5.4 Visual inspection criteria may be specified as a

group according to the standard values listed in the

applicable SEMI specification, or they may be specified

individually.

5.5 For either dimensional values or visual inspection

criteria, the appropriate SEMI specification may be

marked and an optional line item (or items) marked as

well. In this case, the value marked on each individual

line item takes precedence over the standard value.

5.6 If the suggested form included in this format is not

reproduced and used as a fill-out form, the items and

responses must be adequately identified so that the

information and requirements are clear to all parties.

6 Test Methods

6.1 Measurements shall be made or certifiable to the

ASTM, JEITA, JIS, or DIN standard test method as

cited in Table 1.

6.2 When standard test methods from different

geographic regions are available, the default method

shall be the method in common usage for the region of

the purchaser of the wafer.

6.3 If several different standard test methods for an

item are commonly used within a region, a specific

entry must be made to identify which method of test is

applicable.

6.4 If no standard test method for an item is available,

the test procedure must be specified.

SEMI M18-0704 © SEMI 1990, 2004 7

7 Testing Level and Certification

7.1 Material ordered using this format shall be tested

and/or certified to the limits set forth in the individual

criteria.

7.2 The actual testing level, whether the test is

performed on all wafers, a sample of the wafers, special

test pieces representing all portions of the material, or a

sample of the test pieces, may be specified using this

format.

7.3 In some cases, the material may be certified as

“capable of meeting” certain requirements. In this

context, the supplier is not required to perform the tests

outlined in this format. However, if the purchaser

performs the test and the material fails to meet the

requirement, the material may be subject to rejection.

8 EDI Codes and Sub-Parameter Codes

8.1 The EDI Codes for each parameter are listed in the

following Table. Where necessary for clarity,

additional sub-parameters are listed. These sub-

parameter identify a specific measurement technique or

method to be used.

8.2 If additional codes are required in the future, they

will be added to the table, beginning with the next

available EDI code identifier. This will allow the table

to be rearranged for clarity while maintaining unique

and consistent EDI codes for existing parameters.

Table 2 provides a numerically sorted list of the EDI

Codes.

SEMI Silicon Wafer Specification Form For Order Entry (Page 1)

Part 1 General Information

TEM

NFORMATIO

ate:

Customer Name

Purchase Order Number

Line Number

Item Number

General Specification Number

Revision Level

Part Number/Revision

Part 2 Polished Wafer

CUSTOMER:

ART NUMBER: REVISION

ATE:

TESTING LEVEL EDI Sub

WAFER TEST PIECE

Code Param

REQUIRED

ITEM SPECIFICATION

100% SAMP

ID ID

1. GENERAL CHARACTERISTICS

♦

1.1 Growth Method [ ]Cz [ ]FZ [ ]MCz 100001

♦

1.2 Crystal Orientation [ ](100) [ ] (111) [ ] ( ) 100002

♦

1.3 Conductivity Type [ ]p [ ]n 100003

♦

1.4 Dopant [ ]B [ ]Phos [ ]Sb [ ]As [ ]NTD 100004

1.5 Nominal Edge Exclusion

Distance for Fixed

Quality Area

Applies to Sections 6.10–6.14; 11 [ ]3 mm;

[ ]5 mm; [ ]Other__mm

Applies to Sections 7, 8, 12, 13 [ ]3 mm; [ ]5

mm; [ ]Other__mm (except edge defects)

100005

2. ELECTRICAL CHARACTERISTICS

♦

2.1 Resistivity

Nominal [ ] ± Tolerance [ ] Ω−cm

100006

Measurement Position [ ]Center Point; [ ]Other:

Measurement Method [ ]SEMI MF81; [ ]SEMI MF673; [ ]JIS H 612;

[ ]JEIDA 18; [ ]DIN 50431

2.2 Radial Resistivity

Variation (RRG)

Not greater than [ ]% 100007