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SEMI M19-91 © SEMI 1991, 1996 3 3. Con ce ntration dependent: to be agreed upon between us er and producer 4. ≥ 3500 cm 2 /V-s 5. Unspecified B. 1. ≥ 4000 cm 2 /V-s 2. ≥ 2500 cm 2 /V-s 3. ≥ 1500 cm 2 /V-s 4. ≥ 1000 cm 2 …

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SEMI M19-91 © SEMI 1991, 1996 2
scattering, and other related phenomena. Thus, based on
producer experience, the minimum value was set at
3500 cm
2
/V-s.
For n-type materials, the mobility ranges were selected
to represent compensation ratios in the range of
approximately 0.0 to 0.7 for a given net electron
concentration. P-type material is not yet characterized
sufficiently to warrant a specification.
2 Scope
This document specifies the characteristics and ranges
of electrical properties for bulk GaAs crystals and
substrate wafers. For high resistivity and n-type
conducting materials, the permissible growth conditions
or impurity species are stated; the electrical properties
corresponding to the appropriate range(s) are noted.
Due to the limited understanding, experience and
demand for p-type materials only guidelines are
provided in this specification at the present writing.
3 Conductivity Type
A. Semi-insulating, n-type
B. Conducting, n-type
C. Conducting, p-type
4 Dopant Species
A. 1. Undoped; Grade A1
2. Undoped; Grade A2
3. Chromium; Grade A
4. Isoelectronic impurity; Grade A Dopant
specified by producer: In, Al, P, Sb
5. Undoped; Grade B
B. Dopant specified by user: Si, S, Se, Te, Sn
C. Dopant specified by user: Zn, Cd, Be, Mn, Fe, Co,
Mg
NOTE See Sections 4 and 5 below for grade definition.
5 Resistivity at 300K
A. Semi-insulating, n-type*
B. 1. ≥ 1 × 10
7
Ω-cm, n-type before and after anneal
2. ≥ 5 × 10
6
Ω-cm becoming ≥ 1 × 10
7
Ω-cm after
anneal n-type before and after anneal
3. ≥ 1 × 10
7
Ω-cm, n-type before anneal
4. ≥ 1 × 10
7
Ω-cm, n-type before and after anneal
5. ≥ 5 × 10
6
Ω-cm, n-type before and after anneal
1 × 10
7
Ω-cm = 1.6 × 10
8
Ω/❐; 5 × 10
6
Ω-cm = 8 × 10
7
Ω/❐;
* 1 × 10
6
Ω-cm = 1.6 × 10
7
Ω/❐ based on 625 µm
wafer thickness
C. Conducting, n-type
D. 1. ≥ 0.0026 Ω-cm (at n – 4 × 10
16
cm
-3
; µ = 6000
cm
2
/V-s
2. ≤ 0.06 Ω-cm
3. ≤ 0.042 Ω-cm
4. ≤ 0.012 Ω-cm
5. < 5.2 10
-3
Ω-cm
6. to be determined between user and producer
NOTE Ranges overlap due to the interrelationship of ρ, n,
and µ.
E. Ranges to be determined between the user and
producer.
6 Free Carrier or Impurity Concentration
A. 1. Unspecified impurity concentration
2. Unspecified impurity concentration
3. Cr concentration range in atomic ppm specified
by user
4. Isoelectronic impurity concentration range in
atomic ppm specified by producer
5. Unspecified impurity concentration
6. To be determined between user and producer
B. 1. ≤ 4 × 10
16
cm
-3
2. > 4 × 10
16
– 1 × 10
17
cm
-3
3. > 1 × 10
7
– 5 × 10
17
cm
-3
4. > 5 × 10
7
– 3 × 10
18
cm
-3
5. > 3 × 10
18
cm
-3
C. Carrier concentration agreed upon between user and
producer
7 Electron Mobility, 300K (determined by Hall
Effect)
A. 1 ≥ 5000 cm
2
/V-s
2. ≥ 6000 cm
2
/V-s
SEMI M19-91 © SEMI 1991, 19963
3. Concentration dependent: to be agreed upon
between user and producer
4. ≥ 3500 cm
2
/V-s
5. Unspecified
B. 1. ≥ 4000 cm
2
/V-s
2. ≥ 2500 cm
2
/V-s
3. ≥1500 cm
2
/V-s
4. ≥ 1000 cm
2
/V-s
5. ≥ 400 cm
2
/V-s
6. to be determined between user and producer
C. To be agreed upon between user and producer
NOTICE: These standards do not purport to address
safety issues, if any, associated with their use. It is the
responsibility of the user of these standards to establish
appropriate safety and health practices and determine
the applicability of regulatory limitations prior to use.
SEMI makes no warranties or representations as to the
suitability of the standards set forth herein for any
particular application. The determination of the
suitability of the standard is solely the responsibility of
the user. Users are cautioned to refer to manufacturer’s
instructions, product labels, product data sheets, and
other relevant literature respecting any materials
mentioned herein. These standards are subject to
change without notice.
The user’s attention is called to the possibility that
compliance with this standard may require use of
copyrighted material or of an invention covered by
patent rights. By publication of this standard, SEMI
takes no position respecting the validity of any patent
rights or copyrights asserted in connection with any
item mentioned in this standard. Users of this standard
are expressly advised that determination of any such
patent rights or copyrights, and the risk of infringement
of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M20-1104 © SEMI 1991, 2004 1
SEMI M20-1104
PRACTICE FOR ESTABLISHING A WAFER COORDINATE SYSTEM
This practice was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the North American Silicon Wafer Committee. Current edition approved by the North
American Regional Standards Committee on August 16, 2004. Initially available at www.semi.org
September 2004; to be published November 2004. Originally published in 1991; previously published in
2004.
1 Purpose
1.1 Processing systems now employed in advanced
device manufacturing use aligning mechanisms to
position the wafer rotationally and in x-y prior to
processing. Many of these scan the wafer periphery
and determine the geometric center of the wafer
surface. This is most often seen on stepping aligners, to
minimize the effects of wafer-to-wafer diameter
variation in mixed aligner type fabs. Similar center-
referencing subsystems are found on many
characterization systems. The wafer coordinate system
provides a method for referencing any other coordinate
system, such as a site, pattern, or mapping array, to the
physical geometry of the wafer surface.
1.2 If the points of the array lie on the front surface of
the wafer, only the x and y (or r and θ) coordinates are
relevant. It has become increasingly important in
semiconductor material and device manufacturing to
describe, in unambiguous terms, the position of a point
on a wafer that automatic processing, test, or
characterization equipment can recognize and locate.
For example, characterization equipment needs to
report the precise locations of defects and anomalies
discovered in wafers before or after processing in order
to relate the presence or absence of such defects and
anomalies to device yield variations. The wafer
coordinate system can be used to establish the
coordinates of each point of interest, and, through
transformation to the yield analysis coordinate system,
relate them to the die yield map.
1.3 In response to these needs, this practice defines a
wafer coordinate system to facilitate the precise
locating and reporting of points on the wafer surface. If
the point or points lie above or below the surface, the z-
coordinate must also be used. Because the zero point
on the z-axis is application specific, this practice treats
the x-y-z (or r-
-z) system separately from the surface
coordinate system.
2 Scope
2.1 This practice covers procedures for defining a
wafer coordinate system for locating uniquely any point
on a wafer surface using the wafer center as the origin
and either Cartesian (x-y) or polar (r-θ) coordinates.
2.2 For unpatterned wafers, this wafer coordinate
system can be used directly or in conjunction with a
rectangular or polar overlay array.
2.3 This wafer coordinate system can also be used to
locate the origins or other reference points of other
coordinate systems used to define or report position
data of site, die, or map arrays on the front or back
surface of a patterned or unpatterned wafer. In this
way, the array coordinate system may be referenced to
the physical geometry of the wafer. Selected modes of
application of the wafer coordinate system are given for
information only in Related Information 1.
2.4 This practice also covers procedures for defining a
three-dimensional x-y-z (or r-
-z) coordinate system for
the wafer.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Limitations
3.1 Mask alignment conventions are not necessarily
consistent with the wafer coordinate system.
3.2 In SEMI M1, the position of the secondary flat on
silicon wafers is defined by the clockwise rotation from
the primary flat. This is opposite to the convention
used for the polar angle in the wafer coordinate system.
3.3 Also in SEMI M1, the coordinate system for the
edge profile template is, unlike the wafer coordinate
system, edge referenced. In addition, the edge profile
template uses the x coordinate for the radial direction
(positive from the wafer edge inward) and the y
coordinate for the vertical direction (positive from the
wafer surface toward the median plane of the wafer).
3.4 In SEMI E5, the “normal” position of the wafer is
defined similarly to that in the wafer coordinate system;
that is, the primary fiducial is downward and its
bisector is the negative y-axis. However, the rotational
position of the wafer is defined by its clockwise
rotation from the “normal” position, again opposite to
the convention used for the polar angle in the wafer