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SEMI M21-0304 © SEMI 1992, 2004 10 Figure R2-1 Comparison of Array Ad dressing Conventions NOTICE: SEMI makes no warranties or representatio ns as to the suitability of th e standards set forth herein for any particular …

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SEMI M21-0304 © SEMI 1992, 2004 9
RELATED INFORMATION 2
EXTENSIONS TO OTHER ELEMENT ADDRESSING CONVENTIONS
NOTICE: This related information is not an official part of SEMI M21. It was developed during the
original development of the document. This related information was approved for publication by full
letter ballot on October 16, 2003.
R2-1 Element addressing conventions other than that
covered by this guide are also widely used in
engineering. Two of these are illustrated in Figure R2-1
with the use of the same truncated array discussed in
Related Information 1.
R2-2 First-Quadrant Convention
R2-2.1 Addresses in this convention start at the lower
left corner of the array and increase to the right and
upward in the same way as in the convention covered
by this guide. The lower left corner of the array is
defined by the intersection of the bottom boundary of
the lowest row and the left boundary of the leftmost
column. In the case of tiling, the boundaries are those of
the lowest elements and the leftmost elements in the
array. The lower left corner may fall outside the useful
portion of the array. The lower left element of the array
is the element immediately to the right and above the
lower left corner of the array.
R2-2.2 The First-Quadrant Convention uses a column,
row address but does not have a zero row or a zero
column.
R2-2.3 The addresses of the corners of an array with m
columns and n rows in the First-Quadrant Convention
are as follows:
• lower left (Starting Element): (1,1)
• lower right: (m,1)
• upper left: (1,n)
• upper right: (m,n)
R2-2.4 The general formulas for obtaining the
addresses of any element (i
f
,j
f
) in the First-Quadrant
Convention from the addresses (i,j) in the convention
covered by this guide are as follows:
i
f
= i + integer(m/2) + 1
j
f
= j + integer(n/2) + 1
R2-2.5 These equations also apply to arrays with
column or row tiling if n
′
= n or m
′
= m, respectively. If
this condition is not met, the displacement of the row or
column which defines the array centerline with respect
to the boundary of the array must be known to
transform the addresses.
R2-3 Row, Column (Matrix) Convention
R2-3.1 Addresses in this convention start at the upper
left corner of the array and increase to the right and
downward. The upper left corner of the array is defined
by the intersection of the top boundary of the highest
row and the left boundary of the leftmost column. In the
case of tiling, the boundaries are those of the highest
elements and the leftmost elements in the array. The
upper left corner may fall outside the useful portion of
the array. The upper left element of the array is the
element immediately to the right and below the upper
left corner of the array.
R2-3.2 The Row, Column (Matrix) Convention uses a
row, column address and, like the First-Quadrant
Convention, does not have a zero row or a zero column.
R2-3.3 The addresses of the corners of an array with m
columns and n rows in the Row, Column (Matrix)
Convention are as follows:
• upper left (Starting Element): (1,1)
• upper right: (1,m)
• lower left: (n,1)
• lower right: (n,m)
R2-3.4 The general formulas for obtaining the
addresses of any element (i
m
,j
m
) in the Row, Column
(Matrix) Convention from the addresses (i,j) in the
convention covered by this guide are as follows:
i
m
=intege
r
n / 2
(
)
+
1
+
j
j
m
=integer m / 2
(
)
+
1
+
i
R2-3.5 These equations also apply to arrays with
column or row tiling if n
′
= n or m
′
= m, respectively. If
this condition is not met, the displacement of the row or
column which defines the array centerline with respect
to the boundary of the array must be known to
transform the addresses.
SEMI M21-0304 © SEMI 1992, 2004 10
Figure R2-1
Comparison of Array Addressing Conventions
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant
literature respecting any materials mentioned herein. These standards are subject to change without notice.
The user’s attention is called to the possibility that compliance with this standard may require use of copyrighted
material or of an invention covered by patent rights. By publication of this standard, SEMI takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M22-0303 © SEMI 1992, 2003 1
SEMI M22-0303
SPECIFICATION FOR DIELECTRICALLY ISOLATED (DI) WAFERS
This specification was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the North American Silicon Wafer Committee. Current edition approved by the North
American Regional Standards Committee on October 25, 2002. Initially available at www.semi.org
December 2002; to be published March 2003. Originally published in 1992; previously published in
December 1996.
1 Purpose
1.1 Dielectrically isolated (DI) wafers are used for
fabricating specialized semiconductor devices,
including radiation tolerant devices. This specification
is intended to aid the definition and procurement of
such wafers.
2 Scope
2.1 This specification defines requirements for DI
wafers used for semiconductor device manufacture. By
defining inspection procedures and acceptance criteria,
both suppliers and consumers may uniformly define
product characteristics and quality requirements.
NOTE 1: This document currently applies only to DI wafers
with nominal diameter of 100 mm.
2.2 The primary standardized properties set forth in
this specification relate to physical, electrical, and
surface defect parameters of DI wafers.
2.3 A complete purchase specification requires that
additional physical properties be specified along with
suitable test methods for their measurements.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Referenced Standards
3.1 SEMI Standard
SEMI M1 — Specifications for Polished
Monocrystalline Silicon Wafers
3.2 ASTM Standard
1
F 523 — Practice for Unaided Visual Inspection of
Polished Silicon Slices
1 American Society for Testing and Materials, 100 Barr Harbor
Drive, West Conshohocken, Pennsylvania 19428-2959, USA.
Telephone: 610.832.9585, Fax: 610.832.9555 Website:
www.astm.org
3.3 Other Standard
2
ANSI/ASQC Z1.4-1993 — Sampling Procedures and
Tables for Inspection by Attributes
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
4 Terminology
4.1 Definitions
4.1.1 concentricity — The distance between the
centerpoint of the DI wafer and the centerpoint of the
photolithographic pattern.
4.1.2 connected tubs — Adjacent tubs which are not
completely surrounded by an oxide but are connected
by silicon (see Figure 1).
4.1.3 DI wafer — A wafer consisting of polysilicon,
oxide, and single crystal silicon regions. A typical
cross-section is shown in Figure 2.
4.1.4 edge indent — An edge defect on a DI wafer that
extends from the front surface to the back surface.
4.1.5 electrical die — An identifiable repetitive
monolithic combination of tubs and polysilicon areas in
a DI wafer surrounded by a grid border which as
packaged becomes a component.
4.1.6 layer of polycrystalline silicon — The thick
matrix material of a DI wafer in which the silicon tubs
reside.
4.1.7 pattern deformation — A microscopic defect
associated with missing or indented tub features of 4
microns or more (see Figure 3).
4.1.8 rotation — The angle of deviation between the
primary flat of the DI wafer and the x-axis of the
photolithography pattern.
4.1.9 tub — A single crystal silicon region in a DI
wafer which is surrounded by an oxide layer on the
sides and bottom.
2 American National Standards Institute, New York Office: 11 West
42nd Street, New York, NY 10036, USA. Telephone: 212.642.4900;
Fax: 212.398.0023 Website: www.ansi.org