semi合集-English.pdf - 第5188页
SEMI M34-0299 © SEMI 1999 6 7.4.4 Surface Roughness — Surface roughness is a measure of the microscopi c topology of the wafer surface. The effect of t his parameter may be in Gate Oxide Integri ty (GOI) o n MOS devices,…
SEMI M34-0299 © SEMI 1999 5
7.2.2.2 Example 2. Threading dislocation eval-uation
in SIMOX wafers with 170 nm thick top Si layer and
100 nm thick buried oxide: Samples are first immersed
in HF to remove oxide from the surface. Then the
samples are etched for 30 seconds in the solution:
3
50
ml of HF (49%) plus 80 ml of HNO
3
(61%) plus 160 ml
of H
2
O [K
2
Cr
2
O
7
1g + Cu(NO
3
)
2
⋅3H
2
O 4g]. The
thickness of removed silicon is about 1/3 of the initial
top Si layer thickness, i.e., about 60 nm. After rinsing in
water, samples are dipped in HF (49%) for 5 minutes.
The HF etches the buried oxide and creates cavities
under the etch pits. The cavities are around 10 µm in
diameter. Each cavity corresponds to one dislocation
threading the top Si layer. The cavities can be seen at
50X magnification.
7.2.2.3 A recommended protocol for the micro-scopic
etch pit density measurement is to take enough pictures
to count at least 50 etch pits, and then divide the
number counted by the area scanned to get the defect
density. The pictures taken should be non-overlapping
areas of the sample far from the tweezer marks and far
from the edges of the sample. Following is an example
specification: Of the five samples prepared from the test
wafers, none should have threading dislocation
densities higher than 1 × 10
7
cm
-2
.
7.3 Buried Oxide
7.3.1 Buried Oxide Pinhole Measurements — Buried
oxide pinhole evaluations shall be made by CuS0
4
plating or copper decoration methods.
7.3.1.1 In the evaluation done by CuSO
4
plating
method the wafer under study is placed (front face
down) on a paper towel soaked in 20% CuSO
4
solution
on top of a copper plate. An aluminum plate is placed
on the back of the wafer. The copper plate is grounded,
and -25 VDC is applied to the aluminum plate. Small
(sub-micro Angstrom) leakage currents through
pinholes in the insulator cause copper to plate out onto
the towel at the pinhole density.
7.3.1.2 In the evaluation done by copper decoration
method the top Si layer is first etched off by KOH
solution to expose the buried oxide layer. Then the
wafer is immersed in methanol and brought downward
into direct contact with the gold-coated cathode. A
copper mesh as an anode is immersed in the liquid 5
mm above the wafer. Required voltage is applied, such
as the electric field in the buried oxide layer is
1MV/cm. The voltage is measured at the oxide surface
with a surface voltage probe. Localized copper
decorations at pinhole sites in the oxide are observed
with a low power optical microscope.
3 Refer to L. F. Giles, A. Nejim, and P. L. F. Hemment, Materials
Chemistry and Physics, 1993, vol. 35, p. 129
7.3.1.3 Allowable pinhole density depends on the
application for SIMOX wafer and will be determined
by the agreement between user and vendor. Typical
allowable pinhole density is 0.1/cm
2
.
7.4 SIMOX Wafer Surface Inspection
7.4.1 Total Reflectance X-Ray Fluorescence Mea-
surements — The preferred test methodology is
described in ASTM F 1526.
7.4.1.1 The instrument provides a map of impurity
element distribution. As an example specification,
surface contamination for elements within the detection
limits (typically S to Zn) shall be less than 10
10
cm
-2
per
element or < 10
11
cm
-2
total.
7.4.1.2 The customer and vendor should be aware that
most TXRF systems will contaminate a wafer -slightly
on front and significantly on the back. (Reference:
DXRC, Denver CO, July 1996, abstract 5.1 " Particulate
Contamination from TXRF Instru-mentation" , Dennis
Werho, et al.)
7.4.2 Automated Particle Counter Measurements —
Automatic production tools are available for accurate
particle counting on fully processed SIMOX wafers for
particles greater than 0.25 micron. Alternatively,
particles down to 0.1 micron can be detected on as-
implanted SIMOX wafers prior to anneal. Any
specification of particle count should include the point
in the process at which the measurement is to be made.
Following is an example specification:
7.4.2.1 Instrument settings shall allow detection of
particles from 0.3−10 micron size. Maximum allow-
able particle count, with a 6 mm edge exclusion, is 20
particles greater than 0.25 micron size per 150 mm
wafer, or 0.1 particles/cm
2
, just prior to shipping.
7.4.3 Visual and Microscopic Inspection — Visual
inspection techniques will be in accordance with ASTM
F 523, when possible, by automatic inspection
equipment. Alternatively, slices will be inspected
visually under fluorescent light for chips, fractures,
scratches, fragmentation, saw marks, grinder marks,
and dimples and also under a narrow beam high
intensity light (> 6000 footcandles), for fractures, film
haze, contamination, and scratches. SIMOX wafers
typically exhibit uniform light haze due to light
scattering from the rough silicon/oxide interface and
from silicon precipitates in the BOX. A light, uniform
haze is typically acceptable, while patches of moderate
or heavy haze typically are not acceptable.
7.4.3.1 Standards for specification of haze are being
developed for bulk silicon. A modification of that
specification will be required for SIMOX material. It
may be necessary to iterate between customer and
vendor to agree on specification of acceptable haze.
SEMI M34-0299 © SEMI 1999 6
7.4.4 Surface Roughness — Surface roughness is a
measure of the microscopic topology of the wafer
surface. The effect of this parameter may be in Gate
Oxide Integrity (GOI) on MOS devices, depending on
the design and process. The measurement of surface
roughness is done on an atomic scale by an Atomic
Force Microscope (AFM). With AFM, it is suggested
that four measurement areas of greater than 2 µm
2
be
measured at each of five measurement locations, with
the measurement locations distributed as in Figure 1.
Because of the expense of this measurement, a
sampling plan should be established with the supplier.
7.4.4.1 Standards for specification of surface rough-
ness are being developed for bulk silicon and shall be
applicable here when adopted.
7.4.5 HF Defect Measurements - Test Methods
Measurement of the microscopic etch pit density
following an HF etch is a method commonly used to
disclose defects in SOI material. Pitting of the top
silicon surface may be present before the HF etch or be
caused by HF etching. For this destructive
measurement, at least one quarter of a wafer should be
used and preferably a whole wafer. The sample is
placed in concentrated (49%) HF for 10 to 15 minutes,
then removed, rinsed and dried. If there are pits in the
SI surface, metal particles embedded in the surface or
silicides formed in the top Si layer, the HF will etch the
metals/silicides and then etch the buried oxide. This
results in a section of the buried oxide being etched out
that is 25−50 µm diameter (depending on the etch time)
centered on the original pit or particle. The defect
density is then measured in an optical microscope using
a 5X objective and 10X eyepiece or comparable setup.
The sample should be scanned 2−3 times near the
center of the wafer if a whole wafer is used to get
sufficient statistics. If a piece of a wafer is used, the
scan should be adjusted accordingly. The total area
scanned should be at least 10 cm
2
. Care should be taken
to exclude edge density depending on the expected
impact on yield versus material cost. A typical
specification is that the HF defect density should be less
than 1/cm
2
.
SEMI M34-0299 © SEMI 1999 7
Table 1. Specification Summary
Parameter Reference Example Values Method
Wafer diameter (D) ASTM 613 150 mm, 200 mm Optical comparitor
Wafer thickness ASTM 533 Thickness gauge
Thickness variation ASTM 533
< 3 µm
Thickness gauge
Wafer warp ASTM F 657, F 1390
≤ 30 µm for D = 150 mm
Jig + gauge
Crystal orientation ASTM 26 X-ray diffraction
a) front surface
(100) ± 1°
b) back surface
Substrate type/dopant ASTM 42 Hot point probe
Substrate resistivity ASTM 84 4-point probe
Substrate RRG ASTM 84 4-point probe
Surface Si thickness Section 7.1.5 50 nm to 500 nm SE/optical reflectance
Surface Si uniformity Section 7.1.3
± 5 nm
SE/optical reflectance
Buried oxide thickness Section 7.1.6 50 nm to 500 nm SE/optical reflectance
Buried OX uniformity Section 7.1.3
± 10 nm
SE/optical reflectance
Crystal defect (EPD) Section 7.2 < 10 E7/cm
2
SEM examination
Secco etch
Buried OX pinholes < 0.1/cm
2
a) CuSO
4
plating
b) BOX capacitor @ 1 nA
Metal contamination Section 7.4.1 total < 10
11
atoms /cm
2
TXRF
a) per unit area
b) per unit volume
Particles Section 7.4.2
≤ 20 (> 0.25 µm) / wafer
Automated particle counter
Haze Section 7.4.3 See Table 2. Visual inspection
Slip ASTM F 523* See Table 2. Visual inspection
Scratches ASTM F 523* None Visual inspection
Chips ASTM F 523* See Table 2. Visual inspection
Surf Spot Discolor ASTM F 523 See Table 2. Visual inspection
Foreign matter ASTM F 523 See Table 2. Visual inspection
Backside contamination ASTM F 523 Visual inspection
Surface roughness Section 7.4.4 5 Atomic force microscope
(AFM)
Inclusions Section 7.4.5
* The user and supplier may agree on an edge exclusion for these specifications. For example, the area within 6 mm proximity of
the wafer edge may be excluded.