semi合集-English.pdf - 第5282页

SEMI M47-0704 © SEMI 2001, 2004 2 SEMI MF1530 — Standard Test Meth od for Measuring Flatness, Thickness, and Thickness Variation on Silicon Wafers by Autom ated Noncontact Scanning SEMI MF1619 — Standard Test Method for …

100%1 / 7923
SEMI M47-0704 © SEMI 2001, 2004 1
SEMI M47-0704
SPECIFICATION FOR SILICON-ON-INSULATOR (SOI) WAFERS FOR
CMOS LSI APPLICATIONS
This specification technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional
Standards Committee on April 30, 2004. Initially available at www.semi.org June 2004; to be published July
2004. Originally published November 2001; previously published March 2002.
1 Purpose
1.1 This specification defines thin-layer silicon-on-
insulator (SOI) wafer requirements for CMOS large
scale integrated circuit (LSI) devices. In another aspect,
this specification defines the generic characteristics of
SIMOX and bonded silicon-on-insulator wafers having
typically no more than 0.2 µm SOI layer thickness. By
defining parameters, inspection procedures and
acceptance criteria, both users and suppliers may
uniformly define product characteristics and quality
requirements.
2 Scope
2.1 This specification is specifically directed to
SIMOX and bonded silicon-on-insulator wafers, which
are exclusively used for LSI applications made up of
CMOS devices.
2.2 A complete purchase specification requires the
base silicon wafer, SOI surface and layer, and buried
oxide layer properties detailed in this standard, suitable
test methods for their characterization. SEMI M18 may
be for purchase specification purpose.
NOTICE: This standard does not purport to address
safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory or other limitations prior
to use.
3 Referenced Standards
3.1 SEMI Standards
SEMI M1 — Specifications for Polished
Monocrystalline Silicon Wafers
SEMI M11 — Specifications for Silicon Epitaxial
Wafers for Integrated Circuit (IC) Applications
SEMI M18 — Format for Silicon Wafer Specification
From for Order Entry
SEMI M22 — Specifications for Dielectrically Isolated
(DI) Wafers
SEMI M34 — Guide for Specifying SIMOX Wafers
SEMI M35 — Guide for Developing Specifications for
Silicon Wafer Surface Features Detected by Automated
Inspection
SEMI M41 — Specification of Silicon-on Insulator
(SOI) for Power Device/ICs
SEMI MF26 — Standard Test Methods for
Determining the Orientation of a Semiconductive
Single Crystal
SEMI MF42 — Standard Test Methods for
Conductivity Type of Extrinsic Semiconductor
Materials
SEMI MF84 — Standard Test Method for Measuring
Resistivity of Silicon Wafers with an In-Line Four-
Point Probe
SEMI MF523 — Standard Practice for Unaided Visual
Inspection of Polished Silicon Wafer Surfaces
SEMI MF533 — Standard Test Method for Thickness
and Thickness Variation of Silicon Wafers
SEMI MF671 — Standard Test Method for Measuring
Flat Length on Wafers of Silicon and Other Electronic
Materials
SEMI MF928 — Standard Test Methods for Edge
Contour of Circular Semiconductor Wafers and Rigid
Disk Substrates
SEMI MF1152 — Standard Test Methods for
Dimensions of Notches on Silicon Wafers
SEMI MF1188 — Standard Test Method for Interstitial
Atomic Oxygen Content of Silicon by Infrared
Absorption
SEMI MF1241 — Standard Test Methods for
Terminology of Silicon Technology
SEMI MF1390 — Standard Test Method for Measuring
Warp on Silicon Wafers by Automated Noncontact
Scanning
SEMI MF1526 — Standard Test Method for Measuring
Surface Metal Contamination on Silicon Wafers by
Total Reflection X-Ray Fluorescence Spectroscopy
SEMI M47-0704 © SEMI 2001, 2004 2
SEMI MF1530 — Standard Test Method for Measuring
Flatness, Thickness, and Thickness Variation on Silicon
Wafers by Automated Noncontact Scanning
SEMI MF1619 — Standard Test Method for
Measurement of Interstitial Oxygen Content of Silicon
Wafers by Infrared Absorption Spectroscopy with p-
Polarized Radiation Incident at Brewster Angle
SEMI MF2074 — Standards Guide for Measuring
Diameter of Silicon and Other Semiconductor Wafers
3.2 ASTM Standards
1
E122 — Practice for Choice of Sample Size to Estimate
Average Quality of a Lot or Process
F1620 — Standard Practice for Calibrating a Scanning
Surface Inspection System Using Monodisperse
Polystyrene Latex Spheres Deposited on Polished or
Epitaxial Wafer Surfaces
3.3 JEITA Standards
2
JEITA EM-3602 — Standard Specification for
Dimensional Properties of Silicon Wafers with Specular
Surface
JEITA EM-3504
3
(JEIDA 61 in old version) —
Standard Test Method for Interstitial Atomic Oxygen of
Silicon by Infrared Absorption
JEITA EM-3505 — Height calibration in 1 nm order
for AFM
3.4 ANSI Standard
4
ANSI/ASQCZ1.4 — Sampling Procedure and Tables
for Inspection
NOTICE: Unless otherwise indicated, all documents
cited shall be the latest published versions.
4 Terminology
4.1 Many terms relating to silicon technology are
defined in ASTM Terminology F 1241. Other terms
are defined as below.
4.2 Abbreviations and Acronyms
1 American Society for Testing and Materials, 100 Barr Harbor
Drive, West Conshohocken, Pennsylvania 19428-2959, USA.
Telephone: 610.832.9585, Fax: 610.832.9555 Website:
www.astm.org
2 Japanese Electronic and Information Technology Industries
Association, Tokyo Chamber of Commerce and Industry Bldg. 2-2,
Marunouchi 3-chome, Chiyoda-ku, Tokyo 100-0005, Japan. Website:
www.jeita.or.jp
3 Since a new number is assigned, it will be published soon. Until
then, an old version spec number is to be referred.
4 American National Standards Institute, New York Office: 11 West
42nd Street, New York, NY 10036, USA. Telephone: 212.642.4900;
Fax: 212.398.0023 Website: www.ansi.org
4.2.1 BOX — buried oxide layer
4.2.2 SIMOX — separation by implanted oxygen
4.3 Definitions
4.3.1 bonded interface — the plane where the bonding
between handle and device wafers takes place.
4.3.2 bonded wafer — an SOI wafer made by bonding
two silicon wafers with an insulating layer between
them. The insulating layer is typically thermally grown
oxide.
4.3.3 BOX pin-hole — electrically conductive path
through the BOX.
4.3.4 buried oxide layer — the silicon dioxide layer
between SOI layer and base silicon substrate.
4.3.5 handle wafer or base silicon wafer or base
silicon substrate — the substrate which structurally
supports the BOX and the SOI layer.
4.3.6 HF defect — defect in the SOI layer decorated by
immersing the wafer in HF for a certain time.
4.3.7 non-SOI edge area — an annulus between the
nominal radius of the surface silicon layer and the
nominal radius of the base silicon wafer (for bonded
SOI wafers). The annulus which implies an area is
determined by its width as one dimension. It is the
difference in the nominal radius of the surface silicon
layer and the base silicon wafer.
4.3.8 SIMOX wafer — SOI wafer made by oxygen
implantation technology
4.3.9 SOI etch pit — defect in an SOI layer decorated
by immersing the wafer in Secco etch solution.
4.3.10 SOI layer or surface silicon layer — the silicon
layer on the BOX of the SOI wafer.
4.3.11 void — local absence of SOI layer and/or BOX
in bonded wafer.
5 Ordering Information
5.1 Purchase orders for SIMOX or bonded silicon-on-
insulator wafers furnished to this specification shall
include the following items:
• Characteristics for the SOI layer (thickness, crystal
orientation, dopant, etc.)
• Characteristics for the base silicon substrate
(thickness, crystal orientation, dopant, etc.)
• Characteristics of the buried oxide (thickness,
dielectric breakdown voltage, etc.)
• Misalignment of wafer orientation between the SOI
layer and the handle wafer
SEMI M47-0704 © SEMI 2001, 2004 3
• Sampling plan and lot acceptance procedures (see
Section
7)
• Methods of test and measurements (see Section 8)
6 Requirement
6.1 Requirements of SOI wafers consists of a base
silicon wafer specification part and an SOI wafer
specification part. A base silicon wafer is specified
based on a SEMI M18 format. A similar format is
applied for the specification of an SOI wafer.
6.2 As a minimum, the base silicon wafer shall
conform to SEMI M1 and the appropriate individual
polished monocrystalline silicon wafer standard; i.e.
JEITA EM-3602.
6.3 SOI wafer specified items and test methods are
listed in Table 1 and shall not exceed the limits as given
in Table 1.
Table 1 Specification of SOI Wafers for CMOS LSI Applications
Specification Units
Item
SIMOX Bonded
Standard
reference
Test method
Base Silicon Wafer
1. GENERAL CHARACTERISTICS
1.1 Growth Method CZ CZ
1.2 Crystal Orientation
(100) ± 1° (100) ± 1°
SEMI MF26 X-ray diffraction
1.3 Conductivity Type P-type P-type SEMI MF42 Hot point probe
1.4 Dopant Boron Boron
1.5 Edge Exclusion, Nominal 3 (mm) 3 (mm)
2. ELECTRICAL CHARACTERISTICS
2.1 Resistivity (Center Point) See NOTE 1. See NOTE 1. SEMI MF84 4-point probe
3. CHEMICAL CHARACTERISTICS
3.1 Oxygen Concentration See NOTE 1. See NOTE 1. SEMI MF1188,
SEMI MF1619,
JEITA EM-3504
IR absorption
4. STRUCTURAL CHARACTERISTICS
4.2 Slip None None SEMI MF523 Visual inspection
4.3 Lineage None None SEMI MF523 Visual inspection
4.4 Twin None None SEMI MF523 Visual inspection
4.5 Swirl None None SEMI MF523 Visual inspection
4.6 Shallow Pits None None SEMI MF523 Visual inspection
5. WAFER PREPARATION CHARACTERISITICS
5.1 Wafer ID See NOTE 1. See NOTE 1.
5.4 Extrinsic Gettering
Treatment
See NOTE 1. See NOTE 1.
6. MECHANICAL CHARACTERISTICS
Nominal Diameter 150 / 200 (mm) 150 / 200 (mm) SEMI MF2074 6.1
Diameter Tolerance
≤ ± 0.2 (mm) ≤ ± 0.2 (mm)
SEMI MF2074
6.2 Primary Flat
Length/Notch Dimension
SEMI M1 or
JEITA EM-3602
SEMI M1 or
JEITA EM-3602
6.3 Primary Flat/Notch
Orientation
[011] ± 1° [011] ± 1°
SEMI MF671,
SEMI MF1152
6.6 Edge Profile SEMI M1 SEMI M1 SEMI MF928
6.6.1 Edge Surface Finish See NOTE 1. See NOTE 1. SEMI MF928
6.7 Thickness SEMI M1 or
JEITA EM-3602
SEMI M1 or
JEITA EM-3602
SEMI MF533 Thickness gauge
6.8 Thickness Variation
(TTV)
SEMI M1 SEMI M1 SEMI MF533 Thickness gauge
6.14 Flatness Site See NOTE 1. See NOTE 1.