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SEMI M47-0704 © SEMI 2001, 2004 10 scratches, chip s, cracks, pits, di mples, mound, orange peel, voids, LL S and contamination. NOTICE: SEMI makes no warranties or representations as to the suitability o f the standard …
SEMI M47-0704 © SEMI 2001, 2004 9
8.6 BOX Defect
8.6.1 BOX Pinhole Measurement-1 (by CuSO
4
plating
or copper decoration)
8.6.1.1 BOX pinhole evaluations shall be made by
CuSO
4
plating or copper decoration methods. They can
be also evaluated by BOX capacitor dielectric
breakdown, the details of which are explained later in
BOX Pinhole Measurement-2.
8.6.1.2 In evaluation by CuSO
4
plating method, the
sample wafer is placed (front face down) on a paper
towel soaked in 20% CuSO
4
solution on top of a copper
plate. An aluminum plate is placed on the back of the
wafer. The copper plate is grounded, and −25 V
DC
is
applied to the aluminum plate. Small leakage currents
(sub-µA) through pinholes in the BOX cause copper to
plate out onto the towel with the density same as BOX
pinhole density.
8.6.1.3 In evaluation by copper decoration method, an
SOI layer is first etched off by KOH solution to expose
a BOX layer. Then the wafer is immersed in methanol
and brought downward into direct contact with the
gold-coated cathode. A copper mesh as an anode is
immersed in the liquid 5 mm above the wafer. Required
voltage is applied, such as the electric field in the
buried oxide layer is 1 MV/cm. The voltage is
measured at the oxide surface with a surface voltage
probe. Localized copper decorations at pinhole sites in
the oxide are observed with a low power optical
microscope.
8.6.2 BOX Capacitor Dielectric Breakdown — This
parameter can be measured with BOX capacitor. The
BOX thickness affects both the test procedure (such as
capacitor area and voltage criterion) and the allowable
values of measured parameters. These should be
determined by agreement between users and suppliers.
8.6.2.1 Test Structure — BOX capacitor utilizing
mesa-etched SOI layers and Si substrates for both
electrodes to apply electric field to the embedded buried
oxide is used. The area of capacitor, which affects the
breakdown voltage, should be determined by agreement
between users and suppliers. Typical capacitor area is
0.01–0.1 cm
2
. The electrode material and thickness
affect the breakdown phenomena due to thermal effects,
and so should be included in the agreement.
8.6.2.2 Test Method: Staircase I-V Measurement —
Voltage is stepped in one-volt increments from zero to
until destructive breakdown is sensed. The test detects
the onset of high field conduction, as well as the point
of destructive or massive charge injection and trapping.
8.6.3 BOX Pinhole Measurement-2 (by Dielectric
Breakdown)
8.6.3.1 Buried oxide pinhole can be detected also by
BOX capacitor.
8.6.3.2 Test Structure — BOX capacitor having an area
equal to or greater than 0.05 cm
2
.
8.6.3.3 Test Method: Staircase I-V — Measurement
testing can be done for both Type I and Type II defects
where Type I defects are silicon pipes traversing the
buried oxide, and Type II defects are local regions of
thin buried oxide. If Type II defect density is sought,
capacitors are subjected to a series of 30 voltage steps
of 3.3 volts, with current monitored after each step,
using a failure criterion of 1 nA.
8.6.3.4 Any capacitor displaying the failure current or
more for applied field less than 2 MV/cm is considered
defective. Defect density of either type is calculated
from the yield of good capacitors, (Y = 1 − # failed/#
tested), using Poisson statistics;
D = −1n (Y)/A,
where A is the total area of the capacitors tested.
8.7 Particle (LLS : Localized Light Scatterer)
8.7.1 Light Scattering Tomography — The particle
larger than predetermined threshold size is counted by
an automated particle counter.
8.7.2 Principle of Measurement — By scanning the
laser beam on the wafer surface, the light scattered by
particles on a wafer is detected. The scattered light and
the noise from the wafer surface is detected as a direct
current, on the other hand, the scattered light by the
particles can be detected as pulse components. The
particle size can be calibrated with standard polystyrene
latex spheres. SOI wafers usually have scattering noise
from the layer interface. It is necessary to reduce
incident angle of the laser beam to increase the
reflective component from the surface. For example,
S/N ratio is improved when using S-polarized light of
10 degree incident, 85% of its component is reflected
from silicon surface.
NOTE 2: Detailed procedure of size calibration with standard
polystyrene latex spheres: Refer to ASTM F1620.
NOTE 3: Measurement procedure should be determined by
agreement between users and suppliers.
8.8 Visual Inspection — SOI wafer can be visually
inspected in accordance with SEMI MF523. The
automatic inspection equipment is also used when
available. For visual inspection, the collimated high
intensity bright light (e.g. 500,000 lux) is used. Under
using this light, SOI wafer is inspected for haze, slip,
SEMI M47-0704 © SEMI 2001, 2004 10
scratches, chips, cracks, pits, dimples, mound, orange
peel, voids, LLS and contamination.
NOTICE: SEMI makes no warranties or
representations as to the suitability of the standard set
forth herein for any particular application. The
determination of the suitability of the standard is solely
the responsibility of the user. Users are cautioned to
refer to manufacturer’s instructions, product labels,
product data sheets, and other relevant literature
respecting any materials mentioned herein. These
standards are subject to change without notice.
The user’s attention is called to the possibility that
compliance with this standard may require use of copy-
righted material or of an invention covered by patent
rights. By publication of this standard, SEMI takes no
position respecting the validity of any patent rights or
copyrights asserted in connection with any item
mentioned in this standard. Users of this standard are
expressly advised that determination of any such patent
rights or copyrights, and the risk of infringement of
such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
f
the contents in whole or in part is forbidden without express written
consent of SEMI.
SEMI M48-1101 © SEMI 2001 1
SEMI M48-1101
GUIDE FOR EVALUATING CHEMICAL-MECHANICAL POLISHING
PROCESSES OF FILMS ON UNPATTERNED SILICON SUBSTRATES
This guide was technically approved by the Global Silicon Wafer Committee and is the direct responsibility
of the North American Silicon Wafer Committee. Current edition approved by the North American Regional
Standards Committee on August 27, 2001. Initially available at www.semi.org September 2001; to be
published November 2001.
1 Purpose
1.1 The purpose of this document is to provide a guide
for evaluation of chemical-mechanical polishing (CMP)
processes of thin films on unpatterned silicon
substrates. This includes recommended procedures for
process testing and reporting formats.
1.2 This guide is intended for use by both suppliers and
end users.
2 Scope
2.1 This document provides a guide for evaluating a
CMP process for films deposited or grown on an
unpatterned silicon substrate. These evaluations could
include tests with fixed polishing time, fixed removal
rate, fixed ending thickness, time-dependent material
removal, and others.
2.2 Recommended procedures for characterizing a
CMP process are discussed in this guide.
2.3 This guide suggests selected parameters and values
of the properties of the starting monitor wafer.
2.4 This standard does not purport to address safety
issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety health practices and determine the
applicability or regulatory limitations prior to use.
3 Limitations
3.1 The guide does not address evaluation of CMP
processes for films on patterned substrates.
3.2 Evaluation of surface quality or surface
contamination is not addressed in this document.
Surface quality and surface contamination are important
aspects of the CMP process evaluation but they are
beyond the scope of this guide.
3.3 This guide employs sample standard deviation to
estimate variation.
3.4 Wafer positioning precision on a metrology tool
can affect the precision of the polishing evaluation.
This issue is not addressed in this standard.
3.5 The values derived from the calculations in this
guide are sample-dependent. They are affected by
measurement location and number of observations.
4 Referenced Standards
4.1 SEMI Standards
SEMI E89 — Guide for Measurement System
Capability Analysis
SEMI M1 — Specifications For Polished
Monocrystalline Silicon Wafers
SEMI M11 — Specifications For Silicon Epitaxial
Wafers For Integrated Circuit (IC) Applications
SEMI M20 — Specification for Establishing a Wafer
Coordinate System.
4.2 ASTM Standards
1
F 534 — Test Method for Bow of Silicon Slices
F 1390 — Standard Test Method for Measuring Warp
on Silicon Wafers by Automated Noncontact Scanning
F 1530 — Test Method for Measuring Flatness,
Thickness and Thickness Variation on Silicon Wafers
by Automated Noncontact Scanning
F 1618 — Standard Practice for Determination of
Uniformity of Thin Films on Silicon Wafers.
4.3 DIN Standards
2
DIN 50441/4 — Prüfung von Materialen für die
Halbleitertechnologie; Messung der geometrischen
Dimensionen von Halbleiterscheiben;
Scheibendurchmesser und Flattiefe. (Measurement
Determination of the Geometric Dimensions of
Semiconductors Slices [including] Diameter and Flat
Depth)
NOTE 1: Unless otherwise indicated, all documents cited
shall be the latest published versions.
1 American Society for Testing and Materials, 100 Barr Harbor
Drive, West Conshohocken, Pennsylvania 19428-2959, USA.
Telephone: 610.832.9585, Fax: 610.832.9555 Website:
www.astm.org
2 DIN Standards, Deutsches Institut fur Normung e.v., available
from Beuth Verlag GmbH, Burggrafenstrasse 4-10, D-1000 Berlin
30, Germany