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SEMI M57-0705 © SEMI 2004, 2005 10 #2 Test in accordance with SEMI MF951, Plan A1, A2, or A3, as agreed between supplier and custo mer. #3 The value of background carbon concentration is valid only if the crystal is not …

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SEMI M57-0705 © SEMI 2004, 2005 9
Item 180 nm Technology
Generation
130 nm Technology
Generation
90 nm Technology
Generation
5-4 POST-ANNEAL FRONT SURFACE CHEMISTRY
#9
(Surface Metal Concentration)
5-4.1.1 Sodium
1.3 10
10
cm
–2
1.3 10
10
cm
–2
1 10
10
cm
–2
5-4.1.2 Aluminum
1 10
11
cm
–2
1 10
11
cm
–2
1 10
10
cm
–2
5-4.1.3 Potassium
1.3 10
10
cm
–2
1.3 10
10
cm
–2
1 10
10
cm
–2
5-4.1.4 Chromium
1.3 10
10
cm
–2
1.3 10
10
cm
–2
1 10
10
cm
–2
5-4.1.5 Iron
1.3 10
10
cm
–2
1.3 10
10
cm
–2
1 10
10
cm
–2
5-4.1.6 Nickel
1.3 10
10
cm
–2
1.3 10
10
cm
–2
1 10
10
cm
–2
5-4.1.7 Copper
1.3 10
10
cm
–2
1.3 10
10
cm
–2
1 10
10
cm
–2
5-4.1.8 Zinc
1 10
11
cm
–2
1 10
11
cm
–2
1 10
10
cm
–2
5-4.2.1 Calcium
1.3 10
10
cm
–2
1.3 10
10
cm
–2
1 10
10
cm
–2
5-5 POST-ANNEAL FRONT SURFACE INSPECTION CHARACTERISTICS
5-5.1 Slip As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-5.2 Oxidation-Induced Stacking
Faults
As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-5.3 Scratches (macro) None None None
5-5.4 Scratches (micro) – total
length
0.25 diameter 0.25 diameter 0.25 diameter
5-5.5 Haze None by Bright Light
Inspection.
None by Bright Light
Inspection.
None by Bright Light
Inspection.
5-5.6 Total Localized Light
Scatterers, cm
2
0.382 @ 120 nm LSE 0.270 @ 90 nm LSE 0.270 @ 90 nm LSE
5.5.7 Localized Light Scatterers
(COP only), cm
2
As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5.5.8 Other Front Surface
Defects
#10
As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-6 POST-ANNEAL BACK SURFACE INSPECTION CHARACTERISTICS
5-6.1 Contamination/Area As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-6.2 Other Back Surface
Defects
#11
As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-7 POST-ANNEAL OTHER CHARACTERISTICS
5-7.1 Bulk
#12
As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-7.2 Depth of BMD Denuded
Zone
As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-7.3 BMD Density As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
5-7.4 Other Characteristics
#13
As agreed between supplier
& customer.
As agreed between supplier
& customer.
As agreed between supplier
& customer.
#1
Test in accordance with SEMI MF81, Plan B.
SEMI M57-0705 © SEMI 2004, 2005 10
#2
Test in accordance with SEMI MF951, Plan A1, A2, or A3, as agreed between supplier and customer.
#3
The value of background carbon concentration is valid only if the crystal is not intentionally co-doped with carbon (see Item 2-1.7).
#4
200 mm diameter wafers may be used, as agreed between supplier & customer.
#5
Gloss as measured in accordance with ASTM Test Method D 523 or JIS Z 8741 with visible illumination at a 60° angle of incidence
referenced to a mirror polished silicon wafer front surface. This metric may not describe the back surface finish adequately to establish
detectability of small localized light scatterers (LLSs). If it is necessary to detect LLSs smaller than 0.25 µm LSE, another quantitative measure
of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range.
Because a standardized test method has not yet been developed for this metric, both values and test procedures shall be agreed upon between
supplier and customer.
#6
If specified as polished, this term is meant to imply a surface condition and not a particular processing technique. If desired, a quantitative
measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength)
range. Because a standardized test method has not yet been developed for this metric, both values and test procedures, including sampling plan
and detrending procedures, shall be agreed upon between supplier and purchaser.
#7
Warp corrected for gravitational effects. However, warp is not an adequate wafer shape specification for all applications.
#8
Determine in accordance with SEMI MF1530 with the following set up parameters: Site size, 26 mm 8 mm; x-offset = 0 mm; and either %
usable area = 100% with full sites only or % usable area 95% with partial sites included, as per agreement between supplier and customer.
SFQR with a site size of 26 mm × 8 mm is approximately equal to SFSR with a site size of 26 mm × 32 mm. The smaller site allows more
coverage of the FQA than the larger site. The value of site flatness is taken from the ITRS Starting Materials Table.
#9
Surface metal measurement variation can be significant. Measurement results are frequently larger than the actual value. Processes are
normally controlled with median values to reduce the impact of the measurement variation.
#10
Haze, Terracing, Surface micro-roughness, Nanotopography, shallow pits, and other attributes.
#11
Back surface defects that relate to the support (such as, chuck etc.) provided to the back surface of the wafer.
#12
Bulk iron (Fe) may be characterized by SPV technique. For details, refer to SEMI MF391.
#13
Surface boron depletion, dissolved hydrogen in the case of hydrogen annealed wafer, post-annealed oxygen, silicon nitride precipitates and
defects in the case of nitrogen-doped silicon.
7 Sampling
7.1 Unless otherwise specified, ASTM Practice E 122 shall be used to define the sampling plan. When so specified,
appropriate sample sizes shall be selected from each lot in accordance with ANSI/ASQC Z1.4. Each quality
characteristic shall be assigned an acceptable quality level (AQL) or lot tolerance percent defective (LTPD) value in
accordance with ANSI/ASQC Z1.4 definitions for critical, major, and minor classifications. If desired and so
specified in the contract or order, each of these classifications may alternatively be assigned cumulative AQL or
LTPD values. Inspection levels shall be agreed upon between the supplier and the purchaser.
8 Test Methods
8.1 Measurements shall be made or certifiable to one of the SEMI, ASTM, JEITA, JIS, or DIN standard test
methods for the item as selected from the Silicon Wafer Specification Format for Order Entry, Parts 2 and 5, located
in Table 1 of SEMI M1 and Table 1 herein, respectively, and specified in the purchase order.
8.2 If several different standard test methods for an item are commonly used within a region, it is particularly
important that the applicable method of test be identified in the purchase order.
8.3 If no method of test is specified in the purchase order and if standard test methods from different geographic
regions are available, the default method shall be a method in common usage for the region of the purchaser of the
wafer.
8.4 If no standard test method for an item is available, the test procedure to be used must be agreed upon between
supplier and customer.
8.5 Information about the various test methods cited is provided in Related Information 2 of SEMI M1 together
with information about some additional test methods no longer in wide use throughout the industry.
9 Certification
9.1 Upon request of the purchaser in the contract or order, a manufacturer’s or supplier’s certification that the
material was manufactured and tested in accordance with this specification, together with a report of the test results,
shall be furnished at the time of shipment.
9.2 In the interest of controlling inspection costs, the supplier and the customer may agree that the material shall be
certified as “capable of meeting” certain requirements. In this context, “capable of meeting” shall signify that the
SEMI M57-0705 © SEMI 2004, 2005 11
supplier is not required to perform the appropriate tests in §7. However, if the customer performs the test and the
material fails to meet the requirement, the material may be subject to rejection.
10 Product Labeling
10.1 The wafers supplied under these specifications shall be identified by appropriately labeling the outside of each
box or other container and each subdivision thereof in which it may reasonably be expected that the wafers will be
stored prior to further processing. Identification shall include as a minimum the nominal diameter, conductivity
type, dopant, orientation, resistivity range, and lot number. The lot number, either (1) assigned by the original
manufacturer of the wafers, or (2) assigned subsequent to wafer manufacture but providing reference to the original
lot number, shall provide easy access to information concerning the fabrication history of the particular wafers in
that lot. Such information shall be retained on file at the manufacturer’s facility for at least one month after that
particular lot has been accepted by the customer.
10.2 Alternatively, if agreed upon between supplier and customer, one of the box labeling schemes in SEMI T3
shall be used and the information listed in ¶10.1 that is not included on the label shall be retained in the supplier’s
data base for at least one month after that particular lot has been accepted by the customer.
10.3 Wafers of 300 mm diameter shall be shipped in packages labeled in accordance with SEMI M45.
11 Packing and Shipping Container Labeling
11.1 Special packing requirements shall be subject to agreement between the supplier and customer. Otherwise, all
wafers shall be handled, inspected, and packed in such a manner as to avoid chipping, scratches, and contamination
and in accordance with the best industry practices to provide ample protection against damage during shipment.
11.2 Wafers of 300 mm diameter shall be shipped in accordance with SEMI M45.
11.3 Unless otherwise indicated in the purchase order, all outside wafer shipping containers shall be labeled in
accordance with ANSI/EIA 556-B.
NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any
particular application. The determination of the suitability of the standard is solely the responsibility of the user.
Users are cautioned to refer to manufacturer's instructions, product labels, product data sheets, and other relevant
literature, respecting any materials or equipment mentioned herein. These standards are subject to change without
notice.
By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction of
the contents in whole or in part is forbidden without express written
consent of SEMI.