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SEMI M60-0305 © SEMI 2005 1 SEMI M60-0305 TEST METHOD FOR TIME DEPE NDENT DIELECTRI C BREAKDOWN CHARACTERISTICS OF SiO2 FILM S FOR Si WAFER EVALUATION This test method was technically approved by th e Global Silicon Wafe…
SEMI M59-0305 © SEMI 2005 13
6.1.4.1 Discussion — Note that the y-direction associated with the edge profile template in SEMI M1 is in the
vertical direction through the wafer and that this dimension is positive away from the actual surface of the wafer.
6.1.5 z — direction of the wafer coordinate system through the bulk of wafer with the positive direction upwards
when the top surface is up.
NOTE 3: See also ¶6.1.4.1.
6.2 Greek letters
6.2.1 — delta, difference.
6.2.2
— angular direction in a counter clockwise direction from the diameter perpendicular to the bisector of the
primary fiducial in the wafer coordinate system.
6.2.3 — micro, one millionth, usually associated with meters (m) or seconds (s).
6.2.4
— carrier mobility as of an electron or hole in a semiconductor.
6.2.5
— resistivity.
6.2.6
— conductivity.
6.2.7 — ohm, the unit of resistance, combined with a linear dimension, usually centimeter, to be the unit of
resistivity.
6.3 Mathematical symbol
6.3.1 — multiplication sign, also sometimes indicated by a center dot (·) especially when separating various units
in a group of units such as ·cm.
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consent of SEMI.
SEMI M60-0305 © SEMI 2005 1
SEMI M60-0305
TEST METHOD FOR TIME DEPENDENT DIELECTRIC BREAKDOWN
CHARACTERISTICS OF SiO2 FILMS FOR Si WAFER EVALUATION
This test method was technically approved by the Global Silicon Wafer Committee and is the direct
responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional
Standards Committee on January 11, 2005. Initially available at www.semi.org January 2005; to be
published March 2005.
1 Purpose
1.1 The technique outlined in this test method is for the purpose of standardizing silicon wafer characterization by
GOI (Gate Oxide Integrity). For more detailed discussion of the general characterizing methods for this test, the
reader is referred to §3. TZDB technique as SEMI M51 is advantageous to estimate failure rate by intrinsic
breakdown as the C mode and an accidental breakdown as the B mode. However, this test method has a higher
sensitivity for detecting the accidental breakdown mode than TZDB.
2 Scope
2.1 This test method is for the purpose of the characterization method of silicon wafer by GOI. This
characterization method is outlined below
2.1.1 MOS (Metal Oxide Semiconductor) — capacitor fabrication — A gate oxide film is thermally grown on a
silicon wafer surface. Then, poly-Si electrodes are formed on the gate oxide film. Other metals, other than poly-
silicon electrode materials, can be used, however, it shall be desirable to use an electrode that has been confirmed to
have sufficiently good characteristics for application as a gate electrode as described below.
2.1.2 Electrical Characterization Evaluation — The TDDB (Time Dependent Dielectric Breakdown) characteristics
of the MOS capacitors are measured. The presence of COPs (Crystal Originated Particles) at the surface of the
polished Si substrates influences the TDDB characteristics of the gate oxide. That is, the silicon wafer is evaluated
in terms of the TDDB characteristics of the gate oxide. The test method outlined in this test method is for the
purpose of standardizing the procedure of MOS fabrication, measurement, analyses, and the report of the GOI data
to interested parties. This test method is based on the results of round robin among the silicon wafer manufacturers.
In general, GOI strongly depends on crystal defects, contaminations and particles on/near wafer surface. GOI also
depends on the fabrication environment. The cleanliness of the process environment in which the MOS capacitors
are fabricated shall be evaluated to be acceptable (see ¶5.3).
2.2 The target of this test method is to characterize silicon wafers, that is, evaluate COPs near the silicon wafer
surface. The proper gate oxide thickness of the MOS samples is 20–25 nm. A discussion on gate oxide thickness is
given in a later section. Oxygen precipitates are also one of the gate oxide defect origins, however, this is beyond
the scope of this test method because the as-received wafers contain only a small amount of oxygen precipitates.
Near-surface quality can be evaluated in this test. In this case, it is assumed that an oxide film thickness of
approximately 10 nm is used. It is more difficult to categorize the accidental and intrinsic breakdowns in TZDB, as
the gate oxide thickness becomes thinner. Therefore mode classification in TDDB is more effective.
2.3 For detailed discussion on sample structures used in this test method, the reader shall refer to EIA/JEDEC
Standard 35-1. In general, the most likely sample structures are a simple planar MOS (Metal Oxide Semiconductor)
capacitor structure, various isolation structures (for example, LOCOS (LOCal Oxidation of Silicon), STI (Shallow
Trench Isolation)), and FET (Field-Effect Transistor) structures. For the purpose of silicon wafer characterization,
the simple planar MOS capacitor structure is the most desirable. In the case of the various isolation and FET
structures, the silicon wafer receives thermal treatments several times in the complicated sample fabrication process.
Therefore, in this case it is questionable whether the characteristics of the starting Si wafer are reflected in this test
measurement results.
2.4 In this evaluation method, a constant current stress is applied to the gate oxide and time to breakdown is
measured. The amount of charge injected until dielectric breakdown (Q
bd
) is also calculated. (Constant-current
TDDB: detail of measurement condition is described in a later section). The dielectric breakdown by the COPs and
other defects can be evaluated from the accumulated failure distribution of Q
bd
. In addition, a constant-voltage
SEMI M60-0305 © SEMI 2005 2
TDDB method can be used as an evaluation of gate oxide lifetime. In this test method, the constant-current TDDB
method is chosen, because the constant current TDDB method has less influence on parasitic resistance in a
measurement circuit than the constant-voltage TDDB method.
2.5 This test method gives instructions for the procedure for characterizing mirror-polished, p-type CZ silicon
wafers. Gate electrodes were negatively biased so that the silicon surface is in accumulation. Stress current shall be
sufficient for the gate oxide to be broken down within a finite measurement time. In addition, it is desirable to have
an applied current density J within 0.01 and 0.1A/cm
2
.
2.6 The stress gate current has to be reversed for the n-type silicon wafer.
2.7 The poly-silicon film is used as gate electrode of measured MOS capacitors. The poly-silicon film can make
standard test results applicable to the testing of wafers used to fabricate integrated circuits rather than other metal
electrodes because poly-silicon electrodes are commonly used in actual devices. However, a gate electrode other
than poly-silicon gate electrode shall be studied for applications in advanced ultralarge-scale integrated circuits. In
this case, the new electrode material shall have the same detection sensitivity to silicon wafer defects as poly-silicon
electrode.
NOTICE: This test method does not purport to address safety issues, if any, associated with its use. It is the
responsibility of the users of this test method to establish appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
3 Referenced Standards
NOTE 1: When there is no special direction, all the quoted documents are the newest editions.
NOTE 2: When a material other than poly-silicon is used for electrodes, refer to the standard suitable for individual process.
3.1 SEMI Standards
SEMI C3.6 — Standard for Phosphine (PH
3
) in Cylinders, 99.98% Quality
SEMI C3.54 — Gas Purity Guideline for Silane (SiH
4
)
SEMI C21 — Specifications and Guideline for Ammonium Hydroxide
SEMI C27 — Specifications and Guidelines for Hydrochloric Acid
SEMI C28 — Specifications and Guidelines for Hydrochloric Acid
SEMI C30 — Specifications and Guidelines for Hydrogen Peroxide
SEMI C35 — Specifications and Guideline for Nitric Acid
SEMI C38 — Guideline for Phosphorus Oxychloride
SEMI C41 — Specifications and Guidelines for 2-Propanol
SEMI C44 — Specifications and Guidelines for Sulfuric Acid
SEMI C54 — Specifications and Guidelines for Oxygen
SEMI C59 — Specifications and Guidelines for Nitrogen
SEMI M1 — Specifications for Polished Monocrystalline Silicon Wafers
SEMI M51 — Test Method For Characterizing Silicon Wafers by Gate Oxide Integrity.
SEMI MF1241 — Terminology of Silicon Technology (Reapprpved2000)
SEMI MF1771 — Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique
3.2 ASTM Standards
1
ASTM D5127 — Standard Guide for Ultra Pure Water Used in the Electronics and Semiconductor for Industry.
1 American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohocken, Pennsylvania 19428-2959, USA. Telephone:
610.832.9585, Fax: 610.832.9555 Website: www.astm.org