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SEMI M60-0305 © SEMI 2005 2 TDDB met hod can be used as an eval uation of gate oxide lifetime. In this te st method, the constant-current TDDB method is chosen, b ecause the constant cu rrent TDDB method has less influen…

SEMI M60-0305 © SEMI 2005 1

SEMI M60-0305

TEST METHOD FOR TIME DEPENDENT DIELECTRIC BREAKDOWN

CHARACTERISTICS OF SiO2 FILMS FOR Si WAFER EVALUATION

This test method was technically approved by the Global Silicon Wafer Committee and is the direct

responsibility of the Japanese Silicon Wafer Committee. Current edition approved by the Japanese Regional

Standards Committee on January 11, 2005. Initially available at www.semi.org January 2005; to be

published March 2005.

1 Purpose

1.1 The technique outlined in this test method is for the purpose of standardizing silicon wafer characterization by

GOI (Gate Oxide Integrity). For more detailed discussion of the general characterizing methods for this test, the

reader is referred to §3. TZDB technique as SEMI M51 is advantageous to estimate failure rate by intrinsic

breakdown as the C mode and an accidental breakdown as the B mode. However, this test method has a higher

sensitivity for detecting the accidental breakdown mode than TZDB.

2 Scope

2.1 This test method is for the purpose of the characterization method of silicon wafer by GOI. This

characterization method is outlined below

2.1.1 MOS (Metal Oxide Semiconductor) — capacitor fabrication — A gate oxide film is thermally grown on a

silicon wafer surface. Then, poly-Si electrodes are formed on the gate oxide film. Other metals, other than poly-

silicon electrode materials, can be used, however, it shall be desirable to use an electrode that has been confirmed to

have sufficiently good characteristics for application as a gate electrode as described below.

2.1.2 Electrical Characterization Evaluation — The TDDB (Time Dependent Dielectric Breakdown) characteristics

of the MOS capacitors are measured. The presence of COPs (Crystal Originated Particles) at the surface of the

polished Si substrates influences the TDDB characteristics of the gate oxide. That is, the silicon wafer is evaluated

in terms of the TDDB characteristics of the gate oxide. The test method outlined in this test method is for the

purpose of standardizing the procedure of MOS fabrication, measurement, analyses, and the report of the GOI data

to interested parties. This test method is based on the results of round robin among the silicon wafer manufacturers.

In general, GOI strongly depends on crystal defects, contaminations and particles on/near wafer surface. GOI also

depends on the fabrication environment. The cleanliness of the process environment in which the MOS capacitors

are fabricated shall be evaluated to be acceptable (see ¶5.3).

2.2 The target of this test method is to characterize silicon wafers, that is, evaluate COPs near the silicon wafer

surface. The proper gate oxide thickness of the MOS samples is 20–25 nm. A discussion on gate oxide thickness is

given in a later section. Oxygen precipitates are also one of the gate oxide defect origins, however, this is beyond

the scope of this test method because the as-received wafers contain only a small amount of oxygen precipitates.

Near-surface quality can be evaluated in this test. In this case, it is assumed that an oxide film thickness of

approximately 10 nm is used. It is more difficult to categorize the accidental and intrinsic breakdowns in TZDB, as

the gate oxide thickness becomes thinner. Therefore mode classification in TDDB is more effective.

2.3 For detailed discussion on sample structures used in this test method, the reader shall refer to EIA/JEDEC

Standard 35-1. In general, the most likely sample structures are a simple planar MOS (Metal Oxide Semiconductor)

capacitor structure, various isolation structures (for example, LOCOS (LOCal Oxidation of Silicon), STI (Shallow

Trench Isolation)), and FET (Field-Effect Transistor) structures. For the purpose of silicon wafer characterization,

the simple planar MOS capacitor structure is the most desirable. In the case of the various isolation and FET

structures, the silicon wafer receives thermal treatments several times in the complicated sample fabrication process.

Therefore, in this case it is questionable whether the characteristics of the starting Si wafer are reflected in this test

measurement results.

2.4 In this evaluation method, a constant current stress is applied to the gate oxide and time to breakdown is

measured. The amount of charge injected until dielectric breakdown (Q

) is also calculated. (Constant-current

TDDB: detail of measurement condition is described in a later section). The dielectric breakdown by the COPs and

other defects can be evaluated from the accumulated failure distribution of Q

. In addition, a constant-voltage

SEMI M60-0305 © SEMI 2005 2

TDDB method can be used as an evaluation of gate oxide lifetime. In this test method, the constant-current TDDB

method is chosen, because the constant current TDDB method has less influence on parasitic resistance in a

measurement circuit than the constant-voltage TDDB method.

2.5 This test method gives instructions for the procedure for characterizing mirror-polished, p-type CZ silicon

wafers. Gate electrodes were negatively biased so that the silicon surface is in accumulation. Stress current shall be

sufficient for the gate oxide to be broken down within a finite measurement time. In addition, it is desirable to have

an applied current density J within 0.01 and 0.1A/cm

2.6 The stress gate current has to be reversed for the n-type silicon wafer.

2.7 The poly-silicon film is used as gate electrode of measured MOS capacitors. The poly-silicon film can make

standard test results applicable to the testing of wafers used to fabricate integrated circuits rather than other metal

electrodes because poly-silicon electrodes are commonly used in actual devices. However, a gate electrode other

than poly-silicon gate electrode shall be studied for applications in advanced ultralarge-scale integrated circuits. In

this case, the new electrode material shall have the same detection sensitivity to silicon wafer defects as poly-silicon

electrode.

NOTICE: This test method does not purport to address safety issues, if any, associated with its use. It is the

responsibility of the users of this test method to establish appropriate safety and health practices and determine the

applicability of regulatory or other limitations prior to use.

3 Referenced Standards

NOTE 1: When there is no special direction, all the quoted documents are the newest editions.

NOTE 2: When a material other than poly-silicon is used for electrodes, refer to the standard suitable for individual process.

3.1 SEMI Standards

SEMI C3.6 — Standard for Phosphine (PH

) in Cylinders, 99.98% Quality

SEMI C3.54 — Gas Purity Guideline for Silane (SiH

)

SEMI C21 — Specifications and Guideline for Ammonium Hydroxide

SEMI C27 — Specifications and Guidelines for Hydrochloric Acid

SEMI C28 — Specifications and Guidelines for Hydrochloric Acid

SEMI C30 — Specifications and Guidelines for Hydrogen Peroxide

SEMI C35 — Specifications and Guideline for Nitric Acid

SEMI C38 — Guideline for Phosphorus Oxychloride

SEMI C41 — Specifications and Guidelines for 2-Propanol

SEMI C44 — Specifications and Guidelines for Sulfuric Acid

SEMI C54 — Specifications and Guidelines for Oxygen

SEMI C59 — Specifications and Guidelines for Nitrogen

SEMI M1 — Specifications for Polished Monocrystalline Silicon Wafers

SEMI M51 — Test Method For Characterizing Silicon Wafers by Gate Oxide Integrity.

SEMI MF1241 — Terminology of Silicon Technology (Reapprpved2000)

SEMI MF1771 — Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique

3.2 ASTM Standards

ASTM D5127 — Standard Guide for Ultra Pure Water Used in the Electronics and Semiconductor for Industry.

1 American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohocken, Pennsylvania 19428-2959, USA. Telephone:

610.832.9585, Fax: 610.832.9555 Website: www.astm.org

SEMI M60-0305 © SEMI 2005 3

3.3 EIA/JEDEC Standards

2, 3

EIA/JEDEC 35 — Procedure for the Wafer-Level Testing of Thin Dielectrics

EIA/JEDEC 35-1 — General Guidelines for Designing Test Structures for the Wafer-Level Testing of Thin

Dielectrics

EIA/JEDEC 35-2 — Test Criteria for the Wafer-Level Testing of Thin Dielectric

NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.

4 Terminology

4.1 Abbreviations & Acronyms

4.1.1 COP — Crystal Originated Particles

4.1.2 GOI — Gate Oxide Integrity

4.1.3 LOCOS — Local Oxidation of Silicon

4.1.4 MOS — Metal Oxide Semiconductor

4.1.5 STI — Shallow Trench Isolation

4.1.6 TZDB — Time Zero Dielectric Breakdown

4.2 Definitions

4.2.1 Many terms relating to silicon technology are defined in SEMI MF1241.

4.2.2 Definitions for some additional terms are given in SEMI M1 and SEMI MF1771.

4.2.3 Other terms are defined as follows:

4.2.3.1 Crystal Originated Particles

(COP) — This is the one of grown-in defects in the CZ Si wafers with an

octahedral structure. This was found as particles appeared on the silicon surface by repetition SC-1

of RCA

cleaning.

4.2.3.1.1 Discussion — It has been thought that the COP is one of the main origins of the GOI. The gate oxide

formed on the Si surface at which the COP appears easily breaks down at the corner of the octahedral shape like at a

Si trench corner

6,7,8

. This corner of octahedral structures is thinning the oxide films. The oxide electric field

enhances at that place. The breakdown electric field is decreased.

4.2.3.2 Failure Modes — The TDDB Weibull plot

9, 10

is classified to three modes. A typical plot is shown in

Figure 1.

Accidental failure A-A mode

A-B mode

Wearout breakdown W mode

2 Electronic Industries Alliance, EIA Engineering Department, Standards Sales Office, 2001 Eye Street, NW, Washington, D.C. 20006, USA.

Website: www.eia.org

3 Joint Electron Device Engineering Council, 2500 Wilson Blvd., Arlington, VA 22201, website: www.jedec.org

4 J. Ryuta, E. Morita, T. Tanaka and Y. Shimanuki, “Crystal – Originated Singularities on Si Wafer Surface after SC1 Cleaning”, Jpn. J.

Appl. Phys. 29(1990) L947.

5 W. Kern and D. Puotinen, “Clean Solution Based on Hydrogen Peroxide for Use in Silicon Semiconductor Technology”, RCA Rev., 31,

187(1970).

6 T. Mera, J. Jablonski, K. Nagai, and M. Watanabe, “Grown-in defects in silicon crystals responsible for gate oxide integrity deterioration”,

Ohyo-Buturi, 66(7), 728 (1997).

7 K.Yamabe and K.Imai,”Nonplanar Oxidation and Reduction of Oxide Leakage Currents at Silicon Corners by Rounding-off Oxidation”, IEEE

Trans. Electron Devices, ED–34, 1681(1987).

8 K.Yamabe, Y.Shimada, M.Piao, T.Yamazaki, T.Otsuki, R.Takeda, Y.Ohta, S.Jimbo, and M.Watanabe, “Effect of SiO

Thickness on Dielectric

Breakdown Defect Density Due to Surface Crystal–Originated Particles”, J.Electrochem.Soc., 150, F42(2003).

9 D. L. Crook, “Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown”, Proc. Int. Reliability Physics

Symposium, 1979, p.1.

10 E. S. Anolick and G. R. Nelson, “Low Field Time Dependent Dielectric Integrity”, Proc. Int. Reliability Physics Symposium, 1978, p.8.