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SEMI M60-0305 © SEMI 2005 7 Drop o f ap plie d ga te v o lt ag e a t bre a kdow n Brea kd ow n jud gem en t vo l t a g e l e ve l A p plie d G a te Vo lta g e (V) Ti me (s ec ) Drop of applied gate voltage at breakdown B…
SEMI M60-0305 © SEMI 2005 6
5.4.2 Stress Current Density — For reliable measurement, a voltage/current source with a stable output wave shape
shall be used. It is necessary to stabilize the output as much as possible. In the constant current TDDB
measurement, a constant current is continuously applied, and voltage is monitored. The dielectric breakdown is
judged by a sudden drop in the voltage monitored. If the applied stress current density is too low, the time to
breakdown will be too long to be realistic. Contrarily, too a high current density is also unsuitable because the
voltage drop in the oxide breakdown instant becomes small. Considering these factors, the recommended stress
current density range is from 0.01 to 0.1A/cm
2
.
5.5 Measurement Temperature — Besides current density, the measurement temperature is also an important
parameter which determines measurement time. It is appropriate to measure in the temperature range of room
temperature to 150ºC, taking into consideration the temperature tolerance of the measurement equipment. In
addition, there are cases that since silicon wafer, stage chuck, probe, and so on, expand at a high temperature, the
probe deviates from the predetermined position, thus consideration is required when selecting probing machines.
5.6 Breakdown Judgment — To measure the dielectric breakdown lifetime of an oxide film, the voltage applied to a
MOS capacitor is controlled so that a current is kept constant. The applied voltage is monitored throughout the test.
The dielectric breakdown of the oxide is judged by sudden voltage drop. In practice, at the dielectric breakdown the
applied voltage becomes lower than the criterion voltage defined before. The dielectric breakdown lifetime is the
stress application time till breakdown. If the criterion voltage is too low, it can easily affected by noise. In contrast,
the chance of missing breakdown events is increased if the criterion voltage is too high. The changes in two
continuous measured gate voltages can be used to judge the oxide breakdown. The instant at which the voltage
change became larger than the criterion value is defined as dielectric breakdown. The same caution mentioned
above is also required in this case. In this round robin, the current density is from 0.01 to 0.1A/cm
2
, the sheet
resistance of the poly-silicon electrode is approximately 50 ohm/sq, gate electrode area is from 1mm
2
to 10mm
2
,
gate oxide thickness is 25nm and measurement temperature is from room temperature to 150ºC. In this case
dielectric breakdown is determined from the changes in two continuous measured gate voltages. For example, the
change in gate voltage is larger than X
criterion
(%) of the former gate voltage value. X
criterion
is higher than 10%.
Alternatively, dielectric breakdown is determined with the measured electric field, E
ox
. It is considered that
dielectric breakdown does not happen until E
ox
becomes E
criterion
or lower. E
criterion
is higher than 4MV/cm. Stable
measurement results are obtained in both cases. Of course, these criterion electric fields depend on gate oxide
thickness, sheet resistance and area of gate electrode, stress current, stress temperature, and so on. To detect the
dielectric breakdown with the change in gate voltage as shown in Figure 2, it is desirable to determine the criterion
under each condition in advance.
5.7 Estimation of Accidental Failure Rate — As mentioned before, the total number of A-A and A-B mode failures
is related to the crystal quality of the mirror polished CZ Si wafers. It takes a long time to measure the wearout
lifetime of all the MOS capacitors. If a requirement is only measurement of the accidental failure rates of the MOS
capacitors on silicon wafer surface, TDDB measurement can be finished without detecting the wearout lifetimes.
That is, maximum stress time, T
max
, is determined to be Q
bd
in the A-B mode range in advance. The cumulative
failure rate at T
max
is the total failure rate of the A-A and A-B modes. If the rough shapes of the Weibull plots of the
TDDB measurement can be predicted in advance, T
max
shall be determined as to be the maximum Q
bd
in the
relatively flat range of the A-B mode. This reason is that variation of T
max
has little influence on the evaluation of
total accidental failure rates. This method has an advantage of that the failure rate of the A-A and A-B modes is
evaluated very quickly.
5.8 Constant-Voltage TDDB — The constant-voltage TDDB method is also used for a lifetime test. Measurement
conditions shall be optimized for each purpose. For TDDB, an average electric field of approximately 10MV/cm is
required. Therefore, the effective electric field applied to an oxide film is influenced by a series resistance. Thus,
the constant current TDDB is more suitable.
SEMI M60-0305 © SEMI 2005 7
Drop of applied
gate voltage at
breakdown
Breakdown judgement
voltage level
Applied Gate Voltage (V)
Time (sec)
Drop of applied
gate voltage at
breakdown
Breakdown judgement
voltage level
Applied Gate Voltage (V)
Time (sec)
NOTE: A typical applied gate voltage as a function of stress time and a relationship between a drop of the applied gate voltage at
dielectric break-down and breakdown judgment voltage level.
Figure 2
6 Significance and Use
6.1 This standard gives the procedure for characterizing mirror-polished, p-type CZ silicon wafers using the
dielectric breakdown defect densities of the gate oxide thermally grown on them. The MOS capacitors shall be
formed in accordance with the fabrication processes described in §5 and SEMI M51. This reason is because the
oxide characteristics depend on the fabrication processes. If MOS capacitors would be formed with different
fabrication processes, it is desirable to confirm that these GOI results are similar to those of the MOS capacitors
formed by the fabrication processes described above. Particularly, the electrode material of the MOS capacitors has
a great influence on the dielectric breakdown of the gate oxide. Poly-silicon is specified as the electrode material in
this standard. The test with the poly-silicon gate electrode gives us the test results directly applicable to the wafers
for the integrated circuits rather than other metal electrodes, because poly-silicon electrodes are commonly used in
actual devices. Of course other materials are also available for electrodes. Where other electrode material is used,
an appropriate method for each case and the correlation data between poly-silicon and the other material shall be
prepared.
6.2 It is well known that both the silicon surface morphology and the cross-sectional structure at the pattern edge of
the active region of the MOS devices influence the dielectric breakdown of the gate oxide. Various types of
contaminants also influence the dielectric breakdown of the gate oxide. The extent of contamination by alkaline
metals, heavy metals or organic particles increases, as the sample fabrication process progresses.
6.2.1 The electrode area and total number of MOS capacitors shall be chosen to be suitable for the purpose of the
test. The suitable gate area for the constant current TDDB measurement depends on the applied stress (i.e. induced
current). If the gate electrode area is too large, parasitic resistance of the gate electrode disturbs uniform application
of stress current to gate oxide. That is, too a high current density leads to nonuniform stress on gate oxide. As a
result, the reliability of the measurement is reduced. The gate oxide with a defect density is able to be evaluated
using two sets of MOS capacitors. Although the gate area and total number of MOS capacitors have the same
product, one set consists of many capacitors with a small gate area and the other set consists of a few of capacitors
with a large gate area. The TDDB evaluations using the former are more desirable than those using the latter. In
this round robin, where a polycrystalline silicon thickness is 300 nm, sheet resistance is 50/ and gate area is
smaller than 5 mm
2
, reasonable TDDB results were obtained.
7 Interferences
7.1 Since this is a DC measurement, care must be taken to make sure that the silicon wafer has a low-resistance
ohmic contact. There must be no dielectric film on the back surface, e.g., silicon oxide, in order to effectively apply
a voltage bias to the gate oxide. It is not necessary for this to be carried out with a metallic contact on the back
surface of the wafer under test. However, when the vacuum chucking is weak, care must be taken because of the
possibility that the dielectric breakdown of the gate oxide is not accurately judged due to an increase in parasitic
resistance. It is strongly suggested that testing be carried out with a current polarity such that the silicon surface will
be in accumulation below the gate oxide, that is, negative voltages for p-type silicon wafers. If the polarity of the
voltage is chosen to be in the reverse direction, the breakdown voltage may not be accurately measured due to the
presence of a depletion layer below the gate oxide. Controls of electrical noise in this test method are crucial to the
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proper identification of the failure criteria. It is possible that rapid voltage changes at the dielectric breakdown of
the gate oxide cause electrical noise. There is a possibility that this noise leads to misjudgments of the oxide
breakdown. So it is desirable to confirm that oxide breakdown occurred. For example after the TDDB
measurement has been completed, the samples are measured to confirm their insulation. Mechanical stress due to
the exploring probe can influence the measurement results, because the exploring probe is in contact with the gate
electrode directly on the gate oxide. The actual results obtained depend somewhat on the sample fabrication
process. Care must be taken to ensure consistent processing. Wafer temperature during testing shall be clearly
defined. Large temperature variations might have an impact on results.
7.1.1 Precaution — Since the voltages and currents involved are potentially dangerous, appropriate means of
preventing the operator from coming into contact with the exploring probe or other charge surfaces shall be in place
before testing. This standard does not include any clauses relating to the safety and sanitation of the environment.
Those who intend to implement this standard shall consider appropriate means to prevent any accidents or disasters,
as well as taking responsibility for maintaining a state of safety, health and hygiene for users.
8 Sampling
8.1 Sampling is the responsibility of the user of this test method. However, if testing is carried out as part of a
comparison or a correlation, all participants shall agree upon sampling in advance.
NOTE 3: Refer to the appendix of JEDEC standard No.35 for good discussion of sampling plan statistics.
9 Apparatus
9.1 SEMI M51 and SEMI M1771 shall be applied for measurement equipment such as current/voltage source units
and manual probing machines
10 Procedure
10.1 Fabrication of MOS Capacitors
10.1.1 Refer to SEMI M51, introducing poly-silicon as an electrode material. Where another electrode material is
used, an appropriate method for each case and the correlation data between poly-silicon and the other material shall
be prepared.
10.2 Measurement
10.2.1 Before measurement, record the following information for each sample: date, time, operator, sample ID,
oxide thickness, gate area, gate material, oxidation condition, conductivity type (p or n), equipment ID, and
comments.
10.2.2 Decide on measurement parameters and record them. Constant current is applied in this test method. The
parameters include stress current density (J), measurement interval (T
int
), maximum stress time (T
max
), gate area (S),
judgment voltage of breakdown (V
bd
), measurement temperature, the number of capacitors to be measured and a
map of the capacitors.
10.2.3 Set a tungsten exploring probe at the starting position.
10.2.4 Set the exploring probe on a new MOS capacitor at the next position.
10.2.5 Set the accumulated time to zero (T (0) = 0). Record the oxide leakage current and the voltage.
10.2.6 Set the stress current to the designated point. Monitor the time (t) and the voltage (V
t
) from the start.
10.2.7 If the applied time is equal to or greater than the maximum stress time(t T
max
), record the maximum stress
time (T
max
) as the breakdown time (T
bd
) along with the MOS address, and proceed to ¶10.2.8. If t is less than T
max
,
proceed to the next step.
10.2.8 Check to see if the voltage Vt has reached the judgment voltage of breakdown (V
bd
). If so, record the time
(t), along with each MOS address, as the breakdown time (T
bd
), stop applying the stress current, and proceed to
¶10.2.9. If not, repeat from ¶10.2.6.