semi合集-English.pdf - 第5897页

SEMI P38-1103 © SEMI 2002, 2003 9 Table 14 Defect Requi rements for Absorber Stack Class Defect size range (nm) (See Note 1.) Maximum count Defect size range (nm) (See Note 1) Maximum count A1 15–180 0 > 180 0 A2 15–1…

SEMI P38-1103 © SEMI 2002, 2003 8

Table 10 Optical Properties of Buffer Layer and Multilayer Stack

Minimum multilayer stack reflectivity at 150 < λ< 257 nm

(See Note 2.)

55%

Mean buffer layer reflectivity at 190<λ<257 nm (See Notes

1 and 2.)

Agreed upon between user and supplier

Uniformity of buffer layer reflectivity (absolute) (See Note

1.)

Agreed upon between user and supplier

Note 1: Mean is determined from measurements made at different spatial locations on the buffer layer or multilayer stack surface. Sample size

and measurement locations for determining range are to be agreed upon between user and supplier.

Note 2: λ is the inspection wavelength. Reflectivity is specified for < 1% fractional bandwidth at normal incidence

Table 11 Optical Properties of Absorber Stack Surface

Class Mean absorber stack reflectivity at

190<

<257 nm (See Notes 1 and 2.)

Uniformity of reflectivity (absolute)

(See Notes 1 and 2.)

A 5% ± 2%

B 10% ± 1.5%

C 15% ± 1.5%

D 20% ± 1.5%

Note 1: Mean is determined from measurements made at different spatial locations on the absorber stack surface. Sample size and measurement

locations for determining range are to be agreed upon between user and supplier.

Note 2: λ is the inspection wavelength. Reflectivity is specified for < 1% fractional bandwidth and at normal incidence.

Table 12 Properties of the Conductive Layer on the Back Side of the Mask Substrate

Conductive layer properties Requirement

Thickness Agreed upon between user and supplier

Stress Agreed upon between user and supplier

Mechanical durability Agreed upon between user and supplier

Table 13 Defect Requirements for Multilayer Stack

Class PSL equivalent size range

(nm) (See Note 1.)

Maximum defect count

A > 25 0

B > 30 0

C > 40 0

D (Test) > 60 Agreed upon between user and supplier

E (Test) > 90 Agreed upon between user and supplier

Note 1: PSL equivalent size means the detected defect appears to be the same size as a polystyrene latex sphere examined under the same

inspection conditions. Defect count for defects with size smaller than that shown is not specified.

SEMI P38-1103 © SEMI 2002, 2003 9

Table 14 Defect Requirements for Absorber Stack

Class Defect size range (nm) (See

Note 1.)

Maximum count Defect size range (nm) (See

Note 1)

Maximum count

A1 15–180 0 > 180 0

A2 15–180 10 > 180 0

B1 25–265 0 > 265 0

B2 25–265 10 > 265 0

C1 35–360 0 > 360 0

C2 35–360 10 > 360 0

D1 50–520 0 > 520 0

D2 50–520 10 > 520 0

E (Test) < 1000 1500 > 1000 0

Note 1: PSL equivalent size means the detected defect appears to be the same size as a polystyrene latex sphere examined under the same

inspection conditions. Defect count for defects with size smaller than that shown is not specified.

Table 15 Items Included In Mask Blank Label

Item in label Corresponding Table or Figure Included in label for Type 1 (See

Note 1)

Type Table 1 Yes

Layer quality area dimensions, W

followed by D

(to

nearest 0.1 mm)

Figure 2 Yes

Mean median wavelength (to nearest 0.01 nm) Table 4 Yes

Peak reflectivity class of multilayer stack Table 5 Yes

Multilayer stack reflectivity uniformity class Table 6 Yes

Defect quality area dimensions, W

followed by D

(to nearest 0.1 mm)

Figure 3 Yes

Multilayer stack defect class Table 13 Yes

Class for absorber optical properties Table 11 No

Absorber defect class Table 14 No

Note 1: All items in Table 15 are included in the label for mask blank types 2 and 3.

NOTICE: SEMI makes no warranties or representations as to the suitability of the standards set forth herein for any

particular application. The determination of the suitability of the standard is solely the responsibility of the user.

Users are cautioned to refer to manufacturer's instructions, product labels, product data sheets, and other relevant

literature, respecting any materials or equipment mentioned herein. These standards are subject to change without

notice.

By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position

respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this

standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and

the risk of infringement of such rights are entirely their own responsibility.

International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o

the contents in whole or in part is forbidden without express written

consent of SEMI.

SEMI P39-0304

OASIS

– O

PEN ARTWORK SYSTEM INTERCHANGE STANDARD

This standard was technically approved by the Global Micropatterning Committee and is the direct

responsibility of the North American Microlithography Committee. Current edition approved by the North

American Regional Standards Committee on July 12, 2003. Initially available at www.semi.org December

2003; to be published March 2004.

This document was modified in April 2004 to correct editorial errors. Changes were made to Sections 29.8

and 36.2. This document was also editorially modified in July 2004 to correct editorial errors. Changes were

made to Section 36.

1 Purpose

1.1 The purpose of this specification is to define an

interchange and encapsulation format for hierarchical

integrated circuit mask layout information.

1.2 Background — In the fall of 2001, SEMI’s Data

Path Task Force formed a working group to define a

successor to the venerable GDSII Stream format, which

had served the I.C. industry as a de facto standard for

layout interchange for more than two decades. The old

format, limited by 16-bit and 32-bit internal integer

fields, by its inefficient representation of cell-native

geometric figures, and by high structural overhead, was

becoming difficult to use for leading-edge designs, and

file sizes were becoming unwieldy, in some cases

growing to many tens of gigabytes. The successor

format was chartered with several overall goals:

 Achieve at least an order-of-magnitude file size

improvement compared to GDSII Stream.

 Remove all 16-bit and 32-bit integer width

restrictions—make the new format fully 64-bit

capable.

 Efficiently represent cells with large payloads of

flat native geometric figures.

 Provide a richer information palette to facilitate

interchange of layout-related information between

design and manufacturing.

1.2.1 In the months leading up to the formation of the

SEMI Data Path Task Force, International Sematech

sponsored a series of meetings focusing on Mask EDA

issues. Many of the Task Force participants were also

involved in these Sematech meetings, and carried

forward much useful information from those sessions

into the definition of this specification.

2 Scope

2.1 This format is designed primarily to encapsulate

hierarchical mask layout for interchange between

systems such as EDA software, mask writing tools, and

mask inspection/repair tools.

2.2 This format is designed to be both hardware- and

software-independent.

NOTICE: This standard does not purport to address

safety issues, if any, associated with its use. It is the

responsibility of the users of this standard to establish

appropriate safety and health practices and determine

the applicability of regulatory or other limitations prior

to use.

3 Limitations

3.1 Use of extension records such as XNAME,

XELEMENT, and XGEOMETRY may impair

interoperability between tools. It is recommended that

these extensions be used primarily for prototyping, and

that interoperability be maintained through the formal

inclusion of extensions to this specification.

4 Referenced Standards

4.1 IEEE Standards

IEEE 754-1985 — IEEE Standard for Binary Floating-

Point Arithmetic

4.2 ISO Standards

ISO-646-IRV — “US-ASCII” Character Set

ISO-3309 — Information technology —

Telecommunications and information exchange

between systems — High-level data link control

(HDLC) procedures — Frame structure

4.3 IETF Standards

RFC 1951 — DEFLATE Compressed Data Format

Specification version 1.3

1 Institute of Electrical and Electronics Engineers, IEEE Operations

Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, New Jersey

08855-1331, USA. Telephone: 732.981.0060; Fax: 732.981.1721,

Website: www.ieee.org

2 International Organization for Standardization, ISO Central

Secretariat, 1, rue de Varembé, Case postale 56, CH-1211 Geneva 20,

Switzerland. Telephone: 41.22.749.01.11; Fax: 41.22.733.34.30,

Website: www.iso.ch

3 Internet Engineering Task Force, Website: www.ietf.org