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SEMI G61-94 © SEMI 1994 4 3.40 side-t o-side mis alignment — t h e offset of the center li nes of corresponding leads or pins from one side of th e package to another side. 3.41 stand-off — the separat ion bet w e en the…

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SEMI G61-94 © SEMI 19943
of the package that passes through the designed mid-
point of the lead where the lead is attached to the
package (e.g., side-brazed laminates), or where the lead
exits the package body (e.g., plastic dual-in-line
packages). The movement is viewed from the side of
the package, not the ends.
3.24 lead-to-lead separation — the distance between
adjacent leads when measured from their centerlines at
the point of connection to the package.
3.25 lead tweeze — lead movement , measured with
respect to a datum, perpendicular to the top or bottom
of the package that passes through the designed mid-
point of the lead where the lead is attached to the
package (e.g., side-brazed laminates), or where the lead
exits the package body (e.g., plastic dual-in-line
packages). The movement is viewed from the ends of
the package, not the side and the lead movement is
from the edges of the package in toward the centerline
of the package.
3.26 metallization void — the absence of a clad,
evaporated, plated or screen-printed metal layer or
braze from a designated area. Also called metal or
plating void.
3.27 peeling (flaking) — any separation of a plated,
vacuum-deposited, or clad metal layer from the base
metal of a leadframe, pin heatsink, or seal ring, from an
underplate, or from a refractory metal on a ceramic
package. Peeling exposes the underlying metal.
3.28 pin offset — the variation in po sition from the
centerline of the pin to the centerline of the braze pad to
which it is mounted.
3.29 pin sweep — pin movement, measured with
respect to a datum, perpendicular to the top or bottom
of the package that passes through the designed mid-
point of pin where the pin is attached to the package
(e.g., pin grid arrays). The movement is viewed form
the side of the package, not the ends.
3.30 pin-to-pin separation — the distance between
adjacent pins when measured from their centerlines at
the point of connection to the package.
3.31 pin tweeze — pin movement, m easured with
respect to a datum, perpendicular to the top or bottom
of the package that passes through the designed mid-
point of pin where the pin is attached to the package
(e.g., pin grid arrays). The movement is viewed form
the ends of the package, not the side and the pin
movement is from the edges of the package in toward
the centerline of the package.
3.32 pit — in semiconductor packa ges, plastic or
ceramic, or in the leadframes, a shallow depression or
crater. The bottom of the depression must be visible in
order for the term to apply. A pit is formed during
component manufacture (see Figure 3).
3.33 porous surface — an uncompa cted ceramic
surface often showing fine pits.
3.34 projection — on a semiconduc tor package
(plastic or ceramic), leadframe or preform, and
irregularly raised portion of a surface indigenous to the
parent material.
3.35 pullback — on a semiconducto r package, the
linear distance between the edge of a cavity cut into a
ceramic layer and the first measurable glass or
metallization layer interface coated onto the top surface
of that layer. The total pullback may be the result of the
high temperature processing required to manufacture
the package or to coat the surface. It may also be the
result of design considerations (see Figure 5).
3.36 rundown — on a semiconductor package, the
linear distance from the upper surface of a ceramic
cavity layer to the bottom point of the overhang into the
cavity, of a sealing glass or metallization layer that has
been screened onto that surface (see Figure 5).
3.37 scrape — the irregular removal of a deposited
layer from a base material by a shearing action from
another surface such that the base material is exposed
over an extended area. It can also apply to the removal
of surface layers from a material. The material removed
from the scraped area may build up at the edges of the
scrape. The deposited layer may be a metal or glass.
3.38 seal area — on a semiconductor package, the
area designated for sealing a cover or lid to a cofired
ceramic package, or a cap to a cer-DIP or cer-pack
base. In the case of a co-fired ceramic package the seal
area may be either bare ceramic for glass sealing or a
metallized area for solder sealing. The metallized seal
area may be a plating over refractory metallization or a
metal ring, usually iron-nickel-cobalt or iron-nickel
alloys, brazed to the refractory metal.
3.39 seating plane — in plug-in pac kages such as
dual-in-line (side-brazed or cer-DIP) or pin grid arrays,
the plane defined by the three lowest stand-off features
on the lead or pins as measured from the bottom of the
package, or in the absence of these features, by the
package base or mounting plane (see Figure 6). The
features, such as shoulders or projections, hold the
package off the circuit board to which it is mounted.
This gap allows solder flux and residues to be cleaned
after soldering the device and, in some cases, to allow
for sufficient cooling air flow around the device. A
prescribed force is used to hold the device in the
mounting holes when the seating plane is to be
measured.
SEMI G61-94 © SEMI 1994 4
3.40 side-to-side misalignment — the offset of the
center lines of corresponding leads or pins from one
side of the package to another side.
3.41 stand-off — the separation bet ween the base
plane and the seating plane that is created by physical
features that are usually formed into the pins or leads
(see Figure 6). The features may also be called stand-
offs.
3.42 TIR — total Indicator Reading.
4 Ordering Information
Purchase orders for packages furnished to this
specification shall include the following items.
4.1 Current Drawing Revision Detailing
4.1.1 All dimensions and tolerances per ANSI
Y14.5M practices.
4.1.2 Internal metallization trace pattern.
4.1.3 Type and color of ceramic.
4.1.4 Pin or Lead Material and Hardness — If
applicable.
4.1.5 Heat Sink/Stud Material and Hardness — If
applicable.
4.1.6 Type, hardness, and thickness of plating in the
die and wire bond areas and contact pads.
4.1.7 Type, Hardness, and Thickness of Plating on
Pins or Leads and Heat Sink/Stud — If applicable.
4.1.8 Lead Number 1 Identification — (See Figure 7.)
4.2 Vendor certification requirements.
4.3 Reference to this specification.
4.4 Any additions to, or variations from, this
specification.
4.5 Quantity.
5 Dimensions
Package dimensions and lead numbering shall conform
to the outlines registered with or specified by JEDEC
(see Publication 95), EIAJ or MIL-STD-1835, as
appropriate. Package manufacturing tolerances shall be
agreed between user and supplier.
6 Materials
The definitions, defect criteria, and functional tests
described in this specification relate to packages made
with the following materials.
6.1 Ceramic Body
6.1.1 Material — Alumina, beryllia, aluminum nitride,
or mullite as specified on the package drawing.
6.1.1.1 Alumina — Content to be 90% minimum.
6.1.1.2 Beryllia — Content to be 99% minimum.
(Packages shall be marked BeO.)
6.1.1.3 Aluminum nitride — Content t o be agreed
between user and supplier.
6.1.1.4 Mullite — Content to be agree d between user
and supplier.
6.1.2 Color
6.1.2.1 Alumina — White, black, dark brown, or
violet.
6.1.2.2 Beryllia — White.
6.1.2.3 Aluminum Nitride — White, black, dark
brown, or violet.
6.1.2.4 Mullite — White, black, dark brown, or violet.
6.2 Die Attach Pad, Wire Bond Fingers, Contact Pads,
and Circuit Trace Metallization
6.2.1 Base Material — Refractory tungsten per MIL-
M-38510, Type C. Thickness shall be 0.0003" (0.0076
mm) minimum.
6.2.2 Finish — Shall meet the requirements of MIL-
M-38510.
6.2.2.1 Nickel Under Plate (if specified) — Shall be
per QQ-N-290A. Thickness shall be 50 – 350 micro-
inches (0.0013 – 0.0089 mm).
6.2.2.2 Gold Plate — Shall be per MI L-G-45204,
Type III. Thickness shall be 50 – 225 micro-inches
(0.0013 – 0.005715 mm).
6.3 Pins, Leads, and Seal Ring
6.3.1 Base Material — Iron-nickel-cobalt alloy per
MIL-M-38150, Type A or iron-nickel alloy per MIL-
M-38150, Type B shall be specified on the package
drawing.
6.3.2 Hardness — 70–85 Rockwell-B for Type A
material, 60–80 Rockwell-B for Type B material.
6.3.3 Finish — Shall meet the requirements of MIL-
M-38510 per Section 6.2.2.
6.4 Heat Sink/Stud
6.4.1 Material
6.4.1.1 Heat Sink — (Forming at least part of the
package base and the die attach area) tungsten-copper
(composition to be defined on the drawing), iron-nickel
(cobalt) alloy per Section 6.3.1 or molybdenum as
specified on the package drawing.
SEMI G61-94 © SEMI 19945
6.4.1.2 Stud — (Brazed to a metallize d area of the
ceramic base layer or the heatsink of the package) —
copper, tungsten-copper, or kovar as specified on the
package drawing.
6.4.2 Hardness — Shall be specified on the drawing
by agreement between user and supplier.
6.4.3 Finish — Shall meet the requirements of MIL-
M-38510 per Section 6.2.2.
6.5 Braze
6.5.1 Material — Silver/copper (72%/28%) or
equivalent shall meet the general requirements of MIL-
STD-7883.
6.5.2 Finish — Shall meet the requirements of MIL-
M-38510 per Section 6.2.2.
7 Defect Limits
Inspection shall be carried out at 10× magnification
with vertical lighting.
The following conditions are cause for rejection.
7.1 Ceramic Components
7.1.1 Cracks — Any crack is cause for rejection.
7.1.2 Chips — See Figure 3.
7.1.2.1 Corner Chips — Chip sizes ex ceeding the
limits shown in Table 1. No chip may be deeper than
50% of the package element (the ceramic functional
layer) thickness.
Table 1
Package Dimension
inch (mm)
Maximum Corner Chip Dimensions
(either direction) inch (mm)
≤0.250 (≤6.35) 0.020 (0.508)
>0.250 – ≤0.500
(>6.35 – ≤12.7)
0.040 (1.016)
>0.500 – ≤1.000
(>12.7 – ≤25.4)
0.080 (2.032)
>1.000 (>25.4) 0.100 (2.54)
7.1.2.2 Edge Chips — Chip sizes exceeding the limits
shown in Table 2. No chip may be deeper than 50% of
the package element (the ceramic functional layer)
thickness.
Table 2
Package Dimension in which
Chip Occurs inch (mm)
Maximum Chip Length and
Width inch (mm)
≤0.250 (≤6.35) 0.020 (0.508)
>0.250 – ≤0.500
(>6.35 – ≤12.7)
0.040 (1.016)
>0.500 – ≤1.000
(>12.7 – ≤25.4)
0.080 (2.032)
>1.000 (>25.4) 0.100 (2.54)
7.1.2.3 Chips exposing a buried metallized area
excluding the plating buses which are exposed when
packages are separated from the manufacturing arrays.
7.1.2.4 Critical Seal Area (ceramic) — Any chip
reducing the critical seal path length, at any point, by
more than 30% of the nominal design dimension.
No more than three chips, each of which reduces the
seal path length by more than 10% but less than 30%,
are allowed in this area. Each chip’s length shall not
exceed the limits shown in Table 3.
Table 3
Seal Ring Dimension in
which Chip Occurs
inch (mm)
Maximum Chip Length
inch (mm)
≤0.250 (≤6.35) 0.020 (0.508)
>0.250 – ≤0.500
(>6.35 – ≤12.7)
0.040 (1.016)
>0.500 – ≤1.000
(>12.7 – ≤25.4)
0.080 (2.032)
>1.000 (>25.4) 0.100 (2.54)
7.1.3 Ceramic Projections — (bumps and blisters)
7.1.3.1 Body (non-critical surfaces) — Any
projection, including fins, exceeding 0.005" (0.127
mm) in height, or exceeding 0.002" (0.051 mm) in
height and with a surface dimension greater than 0.010"
(0.254 mm).
NOTE 2: On surface mount packages, the bottom of the
package shall not have any projections exceeding 0.002"
(0.051 mm) in height.
7.1.3.2 Die Attach Areas — (bare cera mic or screen
printed metal area) — Excluding a zone, 0.015" (0.381
mm) wide, around the periphery of the cavity, any
projection exceeding 0.001" (0.025 mm) in height or a
surface dimension of 0.010" (0.254 mm).
NOTE 3: Exclusion zones around the periphery of die attach
areas may be wider on larger packages or when a metal heat
sink or stud is brazed to the package and forms the die attach
area (Section 7.3). The width of such zones shall be defined
on the package drawing by agreement between user and