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SEMI G61-94 © SEMI 1994 6 supplier . T his n ote applie s to all c riteria a ffe cting die a ttach areas. 7.1.3.3 Critical Seal Area (printed me t a l area) — Any projection ex ceeding 0.001" (0.025 m m) in height o…

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SEMI G61-94 © SEMI 19945
6.4.1.2 Stud — (Brazed to a metallize d area of the
ceramic base layer or the heatsink of the package) —
copper, tungsten-copper, or kovar as specified on the
package drawing.
6.4.2 Hardness — Shall be specified on the drawing
by agreement between user and supplier.
6.4.3 Finish — Shall meet the requirements of MIL-
M-38510 per Section 6.2.2.
6.5 Braze
6.5.1 Material — Silver/copper (72%/28%) or
equivalent shall meet the general requirements of MIL-
STD-7883.
6.5.2 Finish — Shall meet the requirements of MIL-
M-38510 per Section 6.2.2.
7 Defect Limits
Inspection shall be carried out at 10× magnification
with vertical lighting.
The following conditions are cause for rejection.
7.1 Ceramic Components
7.1.1 Cracks — Any crack is cause for rejection.
7.1.2 Chips — See Figure 3.
7.1.2.1 Corner Chips — Chip sizes ex ceeding the
limits shown in Table 1. No chip may be deeper than
50% of the package element (the ceramic functional
layer) thickness.
Table 1
Package Dimension
inch (mm)
Maximum Corner Chip Dimensions
(either direction) inch (mm)
≤0.250 (≤6.35) 0.020 (0.508)
>0.250 – ≤0.500
(>6.35 – ≤12.7)
0.040 (1.016)
>0.500 – ≤1.000
(>12.7 – ≤25.4)
0.080 (2.032)
>1.000 (>25.4) 0.100 (2.54)
7.1.2.2 Edge Chips — Chip sizes exceeding the limits
shown in Table 2. No chip may be deeper than 50% of
the package element (the ceramic functional layer)
thickness.
Table 2
Package Dimension in which
Chip Occurs inch (mm)
Maximum Chip Length and
Width inch (mm)
≤0.250 (≤6.35) 0.020 (0.508)
>0.250 – ≤0.500
(>6.35 – ≤12.7)
0.040 (1.016)
>0.500 – ≤1.000
(>12.7 – ≤25.4)
0.080 (2.032)
>1.000 (>25.4) 0.100 (2.54)
7.1.2.3 Chips exposing a buried metallized area
excluding the plating buses which are exposed when
packages are separated from the manufacturing arrays.
7.1.2.4 Critical Seal Area (ceramic) — Any chip
reducing the critical seal path length, at any point, by
more than 30% of the nominal design dimension.
No more than three chips, each of which reduces the
seal path length by more than 10% but less than 30%,
are allowed in this area. Each chip’s length shall not
exceed the limits shown in Table 3.
Table 3
Seal Ring Dimension in
which Chip Occurs
inch (mm)
Maximum Chip Length
inch (mm)
≤0.250 (≤6.35) 0.020 (0.508)
>0.250 – ≤0.500
(>6.35 – ≤12.7)
0.040 (1.016)
>0.500 – ≤1.000
(>12.7 – ≤25.4)
0.080 (2.032)
>1.000 (>25.4) 0.100 (2.54)
7.1.3 Ceramic Projections — (bumps and blisters)
7.1.3.1 Body (non-critical surfaces) — Any
projection, including fins, exceeding 0.005" (0.127
mm) in height, or exceeding 0.002" (0.051 mm) in
height and with a surface dimension greater than 0.010"
(0.254 mm).
NOTE 2: On surface mount packages, the bottom of the
package shall not have any projections exceeding 0.002"
(0.051 mm) in height.
7.1.3.2 Die Attach Areas — (bare cera mic or screen
printed metal area) — Excluding a zone, 0.015" (0.381
mm) wide, around the periphery of the cavity, any
projection exceeding 0.001" (0.025 mm) in height or a
surface dimension of 0.010" (0.254 mm).
NOTE 3: Exclusion zones around the periphery of die attach
areas may be wider on larger packages or when a metal heat
sink or stud is brazed to the package and forms the die attach
area (Section 7.3). The width of such zones shall be defined
on the package drawing by agreement between user and
SEMI G61-94 © SEMI 1994 6
supplier. This note applies to all criteria affecting die attach
areas.
7.1.3.3 Critical Seal Area (printed metal area) — Any
projection exceeding 0.001" (0.025 mm) in height or
with a surface dimension exceeding 0.010" (0.254 mm)
or 30% of the critical seal length, whichever is the
larger.
7.1.3.4 Critical Seal Area (bare ceramic) — Any
projection exceeding 0.001" (0.025 mm) in height or
with a surface dimension exceeding 0.010" (0.254 mm)
or 30% of the critical seal path, whichever is the larger.
7.1.3.5 Wire Bond Fingers — Any projection in the
critical area defined in Figure 8 exceeding 0.0005"
(0.0127 mm) in height or a surface dimension of 0.004"
(0.102 mm).
7.1.3.6 Solder Pads, Contact Pads, and Heat
Exchange Areas — Any projection exceeding 0.002"
(0.051 mm) in height above the pad, or a surface
dimension of 0.010" (0.254 mm).
NOTE 4: Castellation areas of chip carriers are excluded from
these criteria because of the manufacturing process. (Layer
misalignments, separation techniques, etc. may cause
projections which do not affect package quality.
7.1.4 Pits
7.1.4.1 Body (non-critical surfaces) — Pits exceeding
0.003" (0.076 mm) in depth or a surface dimension of
0.020" (0.508 mm).
7.1.4.2 Die Attach Areas (bare ceramic or screen
printed metal area) — Excluding a zone, 0.015" (0.381
mm) wide, around the periphery of the cavity, pits
exceeding 0.001" (0.025 mm) depth below the surface
or a surface dimension of 0.010" (0.254 mm).
Acceptable pits shall not cover more than 10% of the
surface area.
NOTE 5: Ceramic pits in metallized areas may be covered by
metallization, but remain cause for rejection.
NOTE 6: Pits with a depth not exceeding 0.0005" (0.0127
mm) are not rejectable.
7.1.4.3 Critical Seal Area (bare ceramic or metallized
area) — Pits exceeding 0.001" (.025 mm) depth below
the ceramic surface or a surface dimension of 0.010"
(0.254 mm). No more than three acceptable pits
allowed in this area with a minimum separation of
0.030" (0.762 mm) required between sites. The seal
ring width must not be reduced by more than 30% of its
designed width at any point. Acceptable pits shall not
cover more than 10% of the critical seal area.
7.1.4.4 Wire Bond Fingers — Any pit in the critical
area defined in Figure 8 exceeding 0.0005" (0.0127
mm) in depth, or any pit exeeding 0.004" (0.102 mm) in
a surface dimension.
7.1.4.5 Solder Pads, Contact Pads, and Heat
Exchange Areas — Pits exceeding 0.002" (0.051 mm)
depth below the pad or a surface dimension of 0.010"
(0.254 mm). Acceptable pits shall not cover more than
10% of the surface area.
NOTE 7: Pits with a depth not exceeding 0.0005" (0.0127
mm) are not included in this evaluation, regardless of surface
dimension.
NOTE 8: Pits in castellation areas are exluded from these
criteria because of the manufacturing process.
7.1.5 Flatness (Camber)
7.1.5.1 Package Flatness — Flatness variation
exceeding 0.004 inch/inch (0.004 mm/mm), with a
minimum camber specification of 0.002" (0.051 mm).
7.1.5.2 Die Attach Area Flatness — Any flatness
variations exceeding the limits shown in Table 4.
NOTE 9: These criteria apply to any die attach area ceramic,
metallized ceramic, or a heat sink which forms the die attach
area.
Table 4
Die Attach Area (Major
Dimension) inch (mm)
Flatness (Maximum
Allowable TIR) inch (mm)
0.750 (#=19.05)
0.002 (0.051)
>0.750 (>19.05) 0.003 inch ( 0.0762 mm)
7.1.5.3 Seal Area Flatness — See Table 5.
NOTE 10: These criteria apply to packages with bare ceramic,
metallized ceramic, or a metal ring. Flatness to be measured
per SEMI G6.
Table 5
Seal Ring (Major
Dimension) inch (mm)
Flatness (Maximum
Allowable TIR) inch (mm)
≤0.500 (≤12.7) 0.002 (0.051)
>0.500 (>12.7 ) 0.003 (0.076)
7.1.6 Delamination — Any evidenc e of delamination
between ceramic layers which exceeds 0.030" (0.762
mm), in a major dimension, in more than two locations.
NOTE 11: Inspection may also be made by scanning acoustic
microscopy per MIL-STD-883, Method 2030, if internal
delamination is suspected. Vendor and customer shall agree
that such inspection is necessary for package integrity.
7.1.7 Foreign Material — Any particulate or film-like
foreign material exceeding 0.005" (0.127 mm) height or
a surface dimension of 0.020" (0.508 mm). No more
than three acceptable sites allowed on the body with a
minimum separation of 0.030" (0.762 mm) required
between sites.
SEMI G61-94 © SEMI 19947
7.1.8 Porous Surface — Packages showing surface
poro-sity per ASTM F 109 shall be subjected to seal
testing per Section 8.2.4 to verify acceptance.
NOTE 12: Surface porosity may cause inconsistent results at
hermeticity testing. Packages which show porosity and fail a
hermeticity test may be evaluated per ASTM E 165 to verify
the acceptance. Inspection may also be made by scanning
acoustic microscopy per MIL-STD-883, Method 2030.
7.2 Metallized Areas on Ceramic
7.2.1 Plating Voids — (Includes voids due to
refractory metal printing defects.)
7.2.1.1 Die Attach Areas — Excluding a 0.015" (0.381
mm) wide zone around the periphery of the cavity,
voids exceeding a surface dimension of 0.020" (0.508
mm). Acceptable voids shall not cover more than 10%
of the surface area.
7.2.1.2 Seal Ring Area — Voids exceeding a surface
dimension of 0.020" (0.508 mm). The seal ring width
must not be reduced by more than 30% of its designed
width at any point. Acceptable voids shall not cover
more than 10% of the seal ring area.
7.2.1.3 Wire Bond Fingers — Any void in the critical
area defined in Figure 8.
7.2.1.4 Internal Lead Traces — Any v oid which
reduces the width of the trace by more than 50% of its
designed width.
NOTE 13: X-ray radiography per MIL-STD-883, Method
2012, or scanning acoustic microscopy per MIL-STD-883,
Method 2030, may be used to verify the integrity of covered
traces.
NOTE 14: Pits are not cause for rejection, providing any
metallization loss does not exceed the 50% criteria.
7.2.1.5 Solder Pads/Castellations or Contact Pads —
Voids with any dimension larger than 0.010" (0.254
mm) or loss of area exceeding 25%. The connection
between a solder pad and the castellation must not be
reduced in width by more than 50% of its design width.
7.2.1.6 Braze Pads — Voids with any dimension
larger than 0.010" (0.254 mm). No more than one
visible, acceptable void per pad is allowable after pin or
lead attachment.
7.2.1.7 Heat Exchange Area — Voids with a surface
dimension larger than 0.020" (0.508 mm). Acceptable
voids shall not cover more than 10% of the heat
exchange area.
7.2.2 Scratches and Scrapes
7.2.2.1 Die Attach Areas — Excluding a 0.015" (0.381
mm) wide zone around the periphery of the cavity, any
buildup of material exceeding 0.001" (0.0254 mm) in
height or exposing base metallization (refractory or
underplate) so that void criteria are violated.
7.2.2.2 Seal Ring Areas — Any buildu p of material
exceeding 0.001" (0.0254 mm) in height or exposing
base metallization (refractory or underplate) so that
void criteria are violated.
7.2.2.3 Wire Bond Fingers — Any scratch in the
critical area defined in Figure 8, which causes
metallization build-up exceeding 0.0005" (0.0127 mm)
in height or a surface dimension of 0.004" (0.102 mm).
In non-critical lead trace areas, any scratch which
exposes base metallization (refractory or underplate)
across more than 50% of the designed trace width.
7.2.2.4 Solder Pads/Castellations — A ny scratch
which isolates more than 25% of a pad from the
castellation by exposure of refractory metallization.
Scrapes must not violate the void criteria of Section
7.2.1.5.
7.2.2.5 Heat Exchange Areas — Any scratches and
scrapes which cause void criteria to be violated (see
Section 7.2.1.7).
7.2.3 Blistering or Peeling of the Metallization — Any
evidence of blistering or peeling.
NOTE 15: Discoloration is not a defect unless a functional
test is affected (e.g., wire bonding) (see Section 8).
7.2.4 Plating Nodules — Nodules exceeding the
criteria for bumps in Sections 7.1.3.2, 7.1.3.3, 7.1.3.4,
and 7.1.3.5.
7.2.5 Refractory Metallization — Pr inting and firing
defects (see Figure 5).
7.2.5.1 Metallized Seal Ring Rundown — Rundown
exceeding 25% of the adjacent internal cavity’s depth.
7.2.5.2 Wire Bond Finger Rundown — Rundown
exceeding 25% of the cavity depth or 0.005" (0.127
mm), whichever is smaller.
7.2.5.3 Wire Bond Finger Pullback — Pullback
exceeding 0.006" (0.152 mm).
7.2.5.4 Metallization Pattern Separation — A
reduction in pattern separation by more than 50% of the
designed separation.
NOTE 16: Pattern separation for chip carrier solder pads may
be further specified by agreement between supplier and
customer to avoid solder shorting during circuit board
assembly.
7.2.5.5 Seal Ring Pullback — Pullback exceeding
0.006" (0.152 mm) from the nominal design location
from both the cavity and package edge directions.
7.2.6 Foreign Material — (Particulate or film-like)