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SEMI G61-94 © SEMI 1994 8 7.2.6.1 D ie Attach Areas (includes ba r e ceramic die attach areas) — Excluding a 0.015" (0.381 mm) wide zone arou nd the periphery of the cavity, any f o reign material exceeding 0.001 &q…

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SEMI G61-94 © SEMI 19947
7.1.8 Porous Surface — Packages showing surface
poro-sity per ASTM F 109 shall be subjected to seal
testing per Section 8.2.4 to verify acceptance.
NOTE 12: Surface porosity may cause inconsistent results at
hermeticity testing. Packages which show porosity and fail a
hermeticity test may be evaluated per ASTM E 165 to verify
the acceptance. Inspection may also be made by scanning
acoustic microscopy per MIL-STD-883, Method 2030.
7.2 Metallized Areas on Ceramic
7.2.1 Plating Voids — (Includes voids due to
refractory metal printing defects.)
7.2.1.1 Die Attach Areas — Excluding a 0.015" (0.381
mm) wide zone around the periphery of the cavity,
voids exceeding a surface dimension of 0.020" (0.508
mm). Acceptable voids shall not cover more than 10%
of the surface area.
7.2.1.2 Seal Ring Area — Voids exceeding a surface
dimension of 0.020" (0.508 mm). The seal ring width
must not be reduced by more than 30% of its designed
width at any point. Acceptable voids shall not cover
more than 10% of the seal ring area.
7.2.1.3 Wire Bond Fingers — Any void in the critical
area defined in Figure 8.
7.2.1.4 Internal Lead Traces — Any v oid which
reduces the width of the trace by more than 50% of its
designed width.
NOTE 13: X-ray radiography per MIL-STD-883, Method
2012, or scanning acoustic microscopy per MIL-STD-883,
Method 2030, may be used to verify the integrity of covered
traces.
NOTE 14: Pits are not cause for rejection, providing any
metallization loss does not exceed the 50% criteria.
7.2.1.5 Solder Pads/Castellations or Contact Pads —
Voids with any dimension larger than 0.010" (0.254
mm) or loss of area exceeding 25%. The connection
between a solder pad and the castellation must not be
reduced in width by more than 50% of its design width.
7.2.1.6 Braze Pads — Voids with any dimension
larger than 0.010" (0.254 mm). No more than one
visible, acceptable void per pad is allowable after pin or
lead attachment.
7.2.1.7 Heat Exchange Area — Voids with a surface
dimension larger than 0.020" (0.508 mm). Acceptable
voids shall not cover more than 10% of the heat
exchange area.
7.2.2 Scratches and Scrapes
7.2.2.1 Die Attach Areas — Excluding a 0.015" (0.381
mm) wide zone around the periphery of the cavity, any
buildup of material exceeding 0.001" (0.0254 mm) in
height or exposing base metallization (refractory or
underplate) so that void criteria are violated.
7.2.2.2 Seal Ring Areas — Any buildu p of material
exceeding 0.001" (0.0254 mm) in height or exposing
base metallization (refractory or underplate) so that
void criteria are violated.
7.2.2.3 Wire Bond Fingers — Any scratch in the
critical area defined in Figure 8, which causes
metallization build-up exceeding 0.0005" (0.0127 mm)
in height or a surface dimension of 0.004" (0.102 mm).
In non-critical lead trace areas, any scratch which
exposes base metallization (refractory or underplate)
across more than 50% of the designed trace width.
7.2.2.4 Solder Pads/Castellations — A ny scratch
which isolates more than 25% of a pad from the
castellation by exposure of refractory metallization.
Scrapes must not violate the void criteria of Section
7.2.1.5.
7.2.2.5 Heat Exchange Areas — Any scratches and
scrapes which cause void criteria to be violated (see
Section 7.2.1.7).
7.2.3 Blistering or Peeling of the Metallization — Any
evidence of blistering or peeling.
NOTE 15: Discoloration is not a defect unless a functional
test is affected (e.g., wire bonding) (see Section 8).
7.2.4 Plating Nodules — Nodules exceeding the
criteria for bumps in Sections 7.1.3.2, 7.1.3.3, 7.1.3.4,
and 7.1.3.5.
7.2.5 Refractory Metallization — Pr inting and firing
defects (see Figure 5).
7.2.5.1 Metallized Seal Ring Rundown — Rundown
exceeding 25% of the adjacent internal cavity’s depth.
7.2.5.2 Wire Bond Finger Rundown — Rundown
exceeding 25% of the cavity depth or 0.005" (0.127
mm), whichever is smaller.
7.2.5.3 Wire Bond Finger Pullback — Pullback
exceeding 0.006" (0.152 mm).
7.2.5.4 Metallization Pattern Separation — A
reduction in pattern separation by more than 50% of the
designed separation.
NOTE 16: Pattern separation for chip carrier solder pads may
be further specified by agreement between supplier and
customer to avoid solder shorting during circuit board
assembly.
7.2.5.5 Seal Ring Pullback — Pullback exceeding
0.006" (0.152 mm) from the nominal design location
from both the cavity and package edge directions.
7.2.6 Foreign Material — (Particulate or film-like)
SEMI G61-94 © SEMI 1994 8
7.2.6.1 Die Attach Areas (includes bare ceramic die
attach areas) — Excluding a 0.015" (0.381 mm) wide
zone around the periphery of the cavity, any foreign
material exceeding 0.001" (0.0254 mm) in height or a
surface dimension of 0.020" (0.508 mm). Acceptable
foreign material shall not cover more than 5% of the die
attach area.
7.2.6.2 Seal Area (includes bare ceramic die attach
areas) — Any foreign material exceeding 0.001"
(0.0254 mm) in height or a surface dimension of 0.020"
(0.508 mm). The seal ring width shall not be reduced by
more than 30% of its width at any point by foreign
material. Acceptable foreign material shall not cover
more than a total of 10% of the seal ring area.
7.2.6.3 Wire Bond Fingers — Any foreign material in
the critical area defined in Figure 8.
7.2.6.4 Solder Pads/Castellations, Contact Pads, and
Heat Exchange Areas — Any foreign material
exceeding 0.001" (0.0254 mm) in height or a surface
dimension of 0.010" (0.254 mm). Acceptable foreign
material shall not cover more than 10% of these areas.
7.3 Pins, Leads, Metal Seal Rings, or Heat Sinks/Studs
NOTE 17: If the heat sink is used as the die attach area, the
following conditions must not violate the criteria in Sections
7.1 and 7.2 for defect size and accumulation.
7.3.1 Plating Voids — Voids, expos ing base material
or underplate, with any dimension exceeding 0.005"
(0.127 mm) or with a total accumulation of more than
5% of the surface area of any pin, lead, heat sink/stud,
or braze. If the total accumulation of voids is less than
5% of the area of an element of a package feature, a
sample of the defective units shall be submitted to Salt
Atmosphere testing per MIL-STD-883, Method 1009,
Condition A. If the sample passes this test, the lot shall
be acceptable
Voids, exposing base material or underplate, in the seal
ring plating violating the criteria of Section 7.2.
7.3.2 Scratches or Scrapes — Any buildup of the
metallization, or exposure of the base material or
underplate, which exceeds 5% of the surface area of
any pin, lead, heat sink/stud, or braze. If the total
accumulation of scratches or scrapes is less than 5% of
the area of an element of the package feature, a sample
of the defective units shall be submitted to salt
atmosphere testing per MIL-STD-883, Method 1009,
Condition A. If the sample passes this test, the lot shall
be acceptable.
7.3.3 Nicks
7.3.3.1 Any nick in pins or leads exce eding 10% of the
diameter or thickness.
7.3.3.2 Any nick in the heat sink/stud which violates
void or pit criteria.
7.3.3.3 Any nicks in the seal ring area which violate
the criteria of Section 7.2.
7.3.4 Pits
7.3.4.1 External Surfaces — Any pit e xceeding 0.005"
(0.127 mm) in depth or 0.010" (0.0254 mm) in a
surface dimension.
Metal seal rings shall have no more than three
acceptable sites, and there must be a minimum
separation of 0.030" (0.762 mm) required between
acceptable sites. The width of the seal ring must not be
reduced by more than 30% of its designed width at any
point. Acceptable pits shall not cover more than 5% of
heat sinks/studs. Acceptable pits shall not cover more
than 25% of pins or leads.
7.3.4.2 Internal Surfaces (Die Attach Areas) — Any
pit exceeding 0.001" (0.0254 mm) in depth and
violating the plating void criteria per Section 7.2.1.1.
7.3.5 Plating Nodules — Any nodul e exceeding the
criteria for burrs in Section 7.3.7.
7.3.6 Foreign Material — Any particulate or film-like
(stain) foreign material exceeding 0.001" (0.025 mm) in
height or an accumulation of sites in excess of 5% of
the surface area of any pin, lead, or heat sink/stud. Any
foreign material reducing the separation between two
active metal areas to less than 50% of the designed
separation.
7.3.7 Burrs — Any burr in excess of 0.002" (0.051
mm) height or 0.005" (0.127 mm) in a major
dimension.
7.3.8 Blistering or Peeling — Any evidence of
blistering or peeling.
NOTE 18: Blistering and peeling on a lead frame tie-bar are
acceptable. Discoloration is not cause for rejection unless a
functional test is affected (e.g., solderability).
7.3.9 Corrosion — Any evidence of corrosion.
7.3.10 Braze
7.3.10.1 Excessive Braze — Any separ ation between
active metal areas which is reduced to less than 50% of
the designed separation.
Any excessive braze which interferes with the intended
use of the package (e.g., excessive braze height which
prevents proper seating of a package).
7.3.10.2 Insufficient Fillet — Pin, lead, heat sink/stud
braze areas where more than 25% of the periphery is
not covered by the braze fillet, provided the voided
areas do not extend under the brazed component.
SEMI G61-94 © SEMI 19949
Any pin, lead, heat sink/stud braze areas where more
than 5% of the periphery is not covered by the braze
fillet and any voids extend under the brazed element.
7.3.11 Mechanical Damage
7.3.11.1 Broken, Kinked, or Missing Pins or Leads
7.3.11.2 Twist — Any pin or lead twist ed by more
than 10° from the untwisted condition.
7.3.11.3 Pin or Lead Sweep — Any location of the tip
of the pin or lead exceeding 0.010" (0.0254 mm) away
from the vertical (or horizontal, for flat packs) datum
passing through the mid-point of the pin or lead at the
point of brazing to the contact pad.
7.3.11.4 Pin or Lead Tweeze — Any location of the
tip of the pin or lead exceeding 0.010" (0.0254 mm)
away from the vertical datum passing through the mid-
point of the pin or lead at the point of brazing to the
contact pad.
7.3.11.5 Threads — Any damage to the threads on
studs.
7.4 Package Construction
7.4.1 Pins and Leads — Location.
7.4.1.1 Pin or Lead Offset — Any offset from the pin
or lead true position exceeding 0.005" (0.127 mm).
7.4.1.2 Lead-to-Lead or Pin-to-Pin Separation — Any
separation exceeding 10% of the designed separation,
up to an allowable maximum of 0.010" (0.254 mm).
7.4.1.3 Side-to-Side Misalignment — Any
misalignment exceeding the limits shown in Table 6.
Table 6
Package Type
Maximum Allowable Side-to-Side
Misalignment inch (mm)
Dual-in-Line 0.010 (0.254)
Flat Packs 0.005 (0.127)
Leaded Chip Carriers 0.005 (0.127)
Pin Grid Arrays 0.005 (0.127)
NOTE 19: During inspection, the combination of offset,
separation, and side-to-side misalignment shall also meet
limits agreed between user and supplier.
7.4.2 Ceramic Layer Misalignment — Any
misalignment between layers exceeding 0.005" (0.127
mm) in either the X or Y planes.
7.4.3 Metallization Alignment to Ceramic — Any
misalignment exceeding the limits defined on the
package drawing.
8 Incoming Inspection and Functional Tests
8.1 Incoming Inspection — Packa ges shall be
inspected in the following sequence.
8.1.1 Dimensional inspection to the requirements of
Section 5. All dimensions shall be measured by
techniques agreed between supplier and customer
except as follows:
8.1.1.1 Seal ring flatness shall be measured per SEMI
G6.
8.1.2 Visual inspection per Section 7.
8.1.3 Metallization — Plating.
8.1.3.1 Thickness — Shall be measured by x-ray
fluorescence per ASTM B 568. The location of the
areas to be measured, which include die and wire bond
and seal ring areas, the tolerance and acceptable
standards shall be agreed between user and supplier.
8.1.3.2 Temperature Resistance — Sh all be evaluated
per SEMI G8.
8.1.3.3 Plating Hardness — Die and wire bond and
seal ring areas — shall be measured per ASTM B 578
to limits defined by MIL-G-45204 if specified by
agreement between vendor and customer.
8.1.3.4 Pin, Lead, Solder Castellation, or Solder Pad
Solderability — Shall be tested per SEMI G35.
8.1.4 Pin, Lead, Seal Ring, or Heat Sink/Stud
Hardness — Shall be measured per ASTM E 18 if
specified by agreement between vendor and customer.
8.1.5 Pin or Lead Integrity — Shall be evaluated per
MIL-STD-883, Method 2004.
NOTE 20: After each test, the plating shall be evaluated for
continuity per SEMI G35.
8.1.5.1 Tension — Per Test Condition A except as
shown in Table 7.
Table 7
Pin/Lead Dimension
inches (mm)
Minimum Tension
lbs (kg)
Round Pin
0.008 (0.203) 1.0 (0.455)
0.018 (0.457) 10.0 (4.55)
Rectangular Lead
0.018 ×=0.010
(0.457=×=0.254)
10.0 (4.55)
8.1.5.2 Fatigue — Per Test Condition B2 if specified
by agreement between user and supplier.
8.1.5.3 Torque — Per Test Condition C1 if specified
by agreement between user and supplier.