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SEMI G78-0699 © SE MI 1999 20 Av g Lot Y-Offs et Av g Lot Y-Offs et + 3s Av g Lot Y-Offs et -3s Lower S pec Lim it Upper S pec Lim i t Av erage Di e Y-Offset Figure 8 Y-Offset NOTICE: These st andards do not purport to a…
SEMI G78-0699 © SEMI 199919
A1-1.18.7 Tips for graph making:
• Add gridlines across the X-axis to separate wafers.
• Print all graphs (X and Y, different lots, different probers) with the same scale in X and Y.
• Add a legend to your graphs, so that they will be readable by your “audience” as well as yourself.
Avg Lot X-Offset
Avg Lot X-Offset +3s
Avg Lot X-Offset -3s
Lower Spec Limit
Upper Spec Limit
Avg Die X-Offset
Figure 7
X-Offset
SEMI G78-0699 © SEMI 1999 20
Avg Lot Y-Offset
Avg Lot Y-Offset +3s
Avg Lot Y-Offset -3s
Lower Spec Limit
Upper Spec Limit
Average Die Y-Offset
Figure 8
Y-Offset
NOTICE: These standards do not purport to address
safety issues, if any, associated with their use. It is the
responsibility of the user of these standards to establish
appropriate safety and health practices and determine
the applicability of regulatory limitations prior to use.
SEMI makes no warranties or representations as to the
suitability of the standards set forth herein for any
particular application. The determination of the
suitability of the standard is solely the responsibility of
the user. Users are cautioned to refer to manufacturer’s
instructions, product labels, product data sheets, and
other relevant literature respecting any materials
mentioned herein. These standards are subject to
change without notice.
The user’s attention is called to the possibility that
compliance with this standard may require use of
copyrighted material or of an invention covered by
patent rights. By publication of this standard, SEMI
takes no position respecting the validity of any patent
rights or copyrights asserted in connection with any
item mentioned in this standard. Users of this standard
are expressly advised that determination of any such
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of such rights, are entirely their own responsibility.
Copyright by SEMI® (Semiconductor Equipment and Materials
International), 3081 Zanker Road, San Jose, CA 95134. Reproduction o
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SEMI G79-0200 © SEMI 20001
SEMI G79-0200
SPECIFICATION FOR OVERALL DIGITAL TIMING ACCURACY
This specification was technically approved by the Global Automated Test Equipment Committee and is the
direct responsibility of the North American Automated Test Equipment Committee. Current edition approved
by the North American Regional Standards Committee on September 3, 1999. Initially available at
www.semi.org November 1999; to be published February 2000.
1 Purpose
1.1 This standard is intended to provide a minimum
common definition of timing accuracy specifications
for automatic semiconductor test equipment (ATE).
2 Scope
2.1 The scope of this standard includes all semicon-
ductor ATE capable of digital functional testing. This
standard does not include the following:
• test fixturing errors,
• device insertion errors, and
• ATE performance or capability beyond timing
accuracy.
2.2 This standard’s overall timing accuracy (OTA)
definition serves to simplify automatic test equipment
comparisons and reduce specification ambiguity.
2.3 This standard does not purport to address safety
issues, if any, associated with its use. It is the responsi-
bility of the users of this standard to establish appro-
priate safety and health practices and determine the
applicability of regulatory limitations prior to use.
3 Limitations
3.1 Parameters associated with the following items are
not covered by the Overall Digital Timing Accuracy
Specification:
• minimum driver pulse width,
• comparator bandwidth,
• I/O round trip delay,
• test fixturing errors,
• device insertion errors,
• time measurement unit accuracy, and
• ATE capability or performance beyond timing
accuracy.
4 Referenced Standards
None.
5 Terminology
5.1 Abbreviations and Acronyms
5.1.1 ATE — automatic test equipment
5.1.2 DUT — device under test
5.1.3 NR — Non-return signal format
5.1.4 RTx — return to zero, one or complement signal
format.
5.1.5 SBx — surround by zero, one or complement
signal format.
5.1.6 Z — driver off (high impedance)
5.2 Definitions
5.2.1 device insertion errors — error influenced by
device-input capacitance and/or terminations.
5.2.2 edge — time delay created by an ATE delay
generation resource.
5.2.3 performance board — printed circuit board used
to interface the tester channels to the device under test.
5.2.4 pin — tester channel
5.2.5 reference load A — 500 ohms in parallel with
2.5pf (± 0.5pf) to ground
5.2.6 reference load B — 50 ohms to ground
5.2.7 reference load C —
• 50 ohms to low (for driver z to high and high to z
transitions).
• 50 ohms to high (for driver z to low and low to z
transitions).
5.2.8 strobe compare — monitor DUT output at a
single time point.
5.2.9 test cycle — inverse of test pattern execution
frequency.
5.2.10 test fixturing errors — error influenced by
mismatched signal path lengths, impedance discontinu-
ities, lumped capacitance/inductance elements, and high
frequency loss due to skin effect or interconnects.
5.2.11 window compare — monitor DUT continuously
during a time interval.