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SEMI G79-0200 © SE MI 2000 5 control tim ing edge, any Z transition for m at, and any test cycle length. NOTE 3: This de finition does not include I /O timing restri ctions imposed by the round tr ip delay between the te…

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SEMI G79-0200 © SEMI 2000 4
7.1.2.4 Output Timing Jitter— short term (cycle to
cycle) instability using any pin, any compare timing
edge, window or strobe compare mode, expect H or L.
Conditions:
• error expressed as RMS value;
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board; and
• jitter referenced to an independent synchronous
trigger.
7.1.3 Input to Output Timing Accuracy — relative
time difference between the average of minimum and
maximum drive input delay timing and the average of
minimum and maximum compare output delay timing.
7.1.3.1 Input to Output Timing Error @ 5V — relative
time difference between the average of minimum and
maximum input delay timing error @ 5V (Section
7.1.1.1) and the average of minimum and maximum
output timing delay error @ 5V (Section 7.1.2.1).
Conditions:
• (same as Sections 7.1.1.1 and 7.1.2.1).
7.1.3.2 Input to Output Timing Error @ 3V — same as
Section 7.1.3.1 using 3V input signal and definitions/
conditions specified in Sections 7.1.1.2 and 7.1.2.2.
7.1.3.3 Input to Output Timing Error @ 1V — same as
Section 7.1.3.1 using 1V input signal and definitions/
conditions specified in Sections 7.1.1.3 and 7.1.2.3.
7.1.4 High Speed Clock Accuracy — DUT high speed
clock input timing error (if different than normal tester
input channels) comprised of high speed clock delay
error, high speed clock self-trigger cycle jitter, high
speed clock self-trigger phase jitter and high speed
clock transition time variation.
7.1.4.1 High Speed Clock Delay Error @ 5V — time
delay at the midpoint of a 5V transition, with respect to
an ideal delay (NIST traceable delay reference), using
any pin, any delay value, any input timing edge, RTZ
format, and any test cycle length.
Conditions:
• delays are normalized to pin 1 (first tester pin),
rising edge, NR format, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load A; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
7.1.4.2 High Speed Clock Delay Error @ 3V — (same
as Section 7.1.4.1 @ 3V)
7.1.4.3 High Speed Clock Delay Error @ 1V — (same
as 7.1.4.1 @ 1V)
7.1.4.4 High Speed Clock Self-trigger Cycle Jitter —
short term instability using any high speed clock pin,
from a rising clock edge to the next rising clock edge,
or falling clock edge to the next falling clock edge.
Conditions:
• error expressed as RMS value;
• reference load B; and
• physical reference point is a zero length
interconnect on the DUT side of a standard
performance board.
7.1.4.5 High Speed Clock Self-trigger Phase Jitter —
short term instability using any high speed clock pin,
from a rising clock edge to the next falling clock edge,
or falling clock edge to the next rising clock edge.
Conditions:
• error expressed as RMS value;
• reference load B; and
• physical reference point is a zero length
interconnect on the DUT side of a standard
performance board.
7.1.4.6 High Speed Clock Transition Time Variation
@ 5V — minimum and maximum rise and fall times of
a 5V input signal transition using any high speed clock
pin.
Conditions:
• referenced to the 20% and 80% points of a positive
and negative signal transition;
• reference load A; and
• physical reference point is a zero length
interconnect on the DUT side of a standard.
7.1.4.7 High Speed Clock Transition Time Variation
@ 3V — (same as Section 7.1.4.6 @ 3V)
7.1.4.8 High Speed Clock Transition Time Variation
@ 1V — (same as Section 7.1.4.6 @ 1V)
7.1.5 Input Timing Delay Error for Z to Drive
High/Low — Time delay error at the midpoint of a
driver transition from Z to high/low, with respect to an
ideal delay, using any pin, any delay value, any Z
SEMI G79-0200 © SEMI 20005
control timing edge, any Z transition format, and any
test cycle length.
NOTE 3: This definition does not include I/O timing
restrictions imposed by the round trip delay between the tester
electronics and the DUT.
Conditions:
• delays are normalized to pin1 (first tester pin),
rising edge, NR format, 5V, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load C; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
7.1.6 Input Timing Delay Error for Drive High/Low to
Z — Time delay error at the midpoint of a driver
transition from high/low to Z, with respect to an ideal
delay, using any pin, any delay value, any Z control
timing edge, any Z transition format, and any test cycle
length.
NOTE 4: This definition does not include I/O timing
restrictions imposed by the round trip delay between the tester
electronics and the DUT.
Conditions:
• delays are normalized to pin1 (first tester pin),
rising edge, NR format, 5V, @ 0ns;
• errors are normalized to the average of minimum
and maximum of the error distribution;
• reference load C; and
• physical reference point is a zero length intercon-
nect on the DUT side of a standard performance
board.
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ations as to the suitability of the standard set forth
herein for any particular application. The determination
of the suitability of the standard is solely the
responsibility of the user. Users are cautioned to refer
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data sheets, and other relevant literature respecting any
materials mentioned herein. These standards are
subject to change without notice.
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compliance with this standard may require use of copy-
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mentioned in this standard. Users of this standard are
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rights or copyrights, and the risk of infringement of
such rights, are entirely their own responsibility.
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the contents in whole or in part is forbidden without express written
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SEMI G80-0200 © SEMI 20001
SEMI G80-0200
TEST METHOD FOR THE ANALYSIS OF OVERALL DIGITAL TIMING
ACCURACY FOR AUTOMATED TEST EQUIPMENT
This test method was technically approved by the Global Automated Test Equipment Committee and is the
direct responsibility of the North American Automated Test Equipment Committee. Current edition approved
by the North American Regional Standards Committee on September 3, 1999. Initially available at
www.semi.org December 1999; to be published February 2000.
1 Purpose
1.1 This procedure will define a standard process
whereby any logic integrated circuit (IC) ATE system
can be evaluated for parameters that makeup an AC
timing accuracy specification.
1.2 Application of this procedure will simplify ATE
comparisons, reduce specification ambiguity, simplify
user acceptance procedures, simplify ATE performance
monitoring, and provide a common validation criteria
for ATE suppliers.
2 Scope
2.1 This procedure is intended for analysis of timing
accuracy specifications for all semiconductor automatic
test equipment (ATE) capable of digital functional
testing. The extent of the analysis includes overall
timing accuracy and the primary components of overall
timing accuracy as defined in the definition section of
this document.
2.2 This procedure does not include analysis of the
following parameters associated with ATE timing
accuracy:
• minimum driver pulse width,
• comparator bandwidth,
• I/O round trip delay,
• test fixturing errors,
• device insertion errors,
• time measurement unit (TMU) accuracy, and
• ATE capability or performance beyond AC timing
accuracy.
2.3 Application of this procedure can reduce
equipment acceptance time resulting in savings for both
the end-users and ATE suppliers.
2.4 This standard does not purport to address safety
issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine
the applicability of regulatory limitations prior to use.
3 Limitations
3.1 The following limitations are inherent to this
procedure:
3.1.1 The tolerances of each measurement used in the
procedure are listed in each test, where appropriate.
3.1.2 The verification methods do not include varying
environmental conditions, so results may not reflect
performance at environmental limits.
3.1.2.1 Due to execution time limits, the verification
procedure does not represent an exhaustive analysis.
The number of data points analyzed is intended to pro-
vide a minimum representative assessment of AC tim-
ing accuracy parameters in a practical amount of time.
3.1.3 This method uses only edge compare mode and
non-multiplexed operation in providing a minimum
representative assessment of AC timing accuracy.
3.1.4 This method does not determine the effects that
duty cycle variations have on AC timing accuracy.
3.1.5 Not being an exhaustive analysis this method
avoids comprehensive testing as might be expected for
complex AC timing functions such as on-the-fly (OTF)
timing. This method was defined with the intention of
keeping the data gathering practical such that
meaningful results are obtained in a reasonable amount
of time. In the case of timing-on-the fly a routine is
contained in this method and can be used as a reference
parameter for comparative purposes when systems with
on-the-fly timing are analyzed. Thus only the most
fundamental AC timing results are produced and OTF
timing is not included as part of the overall timing
accuracy (OTA) results.
3.1.6 Discretion is advised when interpreting OTA
results obtained from this method. Self-analysis cannot
allow for all error components to be isolated. Thus good
(compliant) method results should be viewed with cau-
tion as potentially compliant. On the other hand, poor
(non-compliant) method results are a strong indication
that the system under evaluation is questionable
regarding its accuracy and most likely non-compliant.