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SEMI G80-0200 © SE MI 2000 13 to establish Drive Input to Co mpare Output timing error. Ref erence Figure 6. 12.2.6 As noted, Level 1 analysis doe s e stablish drive input to compare output-timing error. But, Level 1 can…

SEMI G80-0200 © SEMI 2000 12

12.1.12 High Speed Clock Transition Time Variation

(Section 10.4.3) — This value is taken from Table 1. It

is the difference between the minimum and maximum

values shown in Table 1 for this parameter.

12.1.13 High Speed Clock Phase Jitter (Section

10.4.6) — This value is taken from Table 1. This is the

RMS values shown in Table 1 for this parameter.

12.1.14 High Speed Clock Accuracy — This

parameter is for systems that have a High Speed Clock

function. High Speed Clock Accuracy is simply the

same entry made for High Speed Clock Delay Error.

High Speed Clock Transition Time Variation, High

Speed Clock Cycle Jitter, and High Speed Clock Phase

Jitter are reference parameters and should be entered to

the appropriate location in Table 2.

12.1.15 Driver Input Z Timing Errors (Section 10.3.5)

— There are four Drive Input Z Timing Errors. Each

value is determined in the same way and is to be

entered into Table 2. This value is taken from Table 1.

Data to enter here is Positive Error and Negative Error

per the data in Table 1 and Equation 1, Appendix 2.

12.1.16 Timing Linearity (Section 10.3.1) — This

value is established from Table 1. Data to enter here is

Positive Error and Negative Error per the data in Table

1 and Equation 1, Appendix 2. These two values

should be entered at the appropriate place in Table 2.

12.1.17 Extended Delay (Section 10.3.4) — This value

is taken from Table 1. Data to enter here is Positive

Error and Negative Error per the data in Table 1 and

Equation 1, Appendix 2.

12.1.18 Multiple Period (Section 10.3.6) — This

parameter is optional. The test method for this

parameter was defined for those systems with Timing

On the Fly (OTF). If the system under evaluation does

not have OTF timing data entry for this parameter is not

required. Else, this value is taken from Table 1. Data

to enter here is Positive Error and Negative Error per

the data in Table 1 and Equation 1, Appendix 2.

12.2 Interpreting Results — Table 2 will contain

summarized data, results of the Overall Digital Timing

Accuracy Analysis Method for automated test systems.

12.2.1 This dialog is intended to explain the Level 1

and Level 2 results for OTA contained in Table 2 and

require reference to Figure 6, Figure 7

, and Table 2.

12.2.2 Level 1 analysis is meant to determine a test

system’s net conformance to the OTA specification in

an efficient manner.

15 Additional information related to Figure 7 is contained in

Appendix 2.

12.2.3 Level 2 employs external equipment to isolate

parameters that contribute to OTA. That data reveals a

more detailed and accurate representation to OTA

conformance. Regardless, there is a limitation at

getting to OTA entirely through Level 2 data collection.

12.2.4 Level 1 and Level 2 parameters are contained

in Table 2 to represent OTA (Overall Timing

Accuracy). Level 1 Timing Linearity (Section 10.3.1)

provides analysis for all pins under comprehensive

conditions and is used to acquire the drive input to

compare output error parameter. Extended Delay

(Section 10.3.4) complements Timing Linearity by

verifying accuracy for timing generator delays beyond

the length of the test cycle, and can be (optionally) used

in lieu of Section 10.3.1. These two Level 1 elements

represent in part OTA. Thus, this method produces a

single point representation of system OTA, per the

methodology defined in this method and consistent with

the definition of OTA. This is done by summing Level

2 Drive Input Edge Placement Accuracy and Compare

Output Edge Placement Accuracy with Level 1 Drive

Input to Compare Output Timing Accuracy.

12.2.4.1 Compare side error in this method is not fully

characterized or broken out into its constituent compo-

nents, per the defintion of Compare Output Edge Place-

ment Error. This method does establish Output Timing

Delay Error, and its measurement contains the jitter

component. But the method does not contain a way for

determining Output Compare Timing Jitter by itself.

12.2.5 Establishing OTA using only Level 2 data is

not possible. Only two of the three components per the

standard definition of OTA can be determined. The

OTA definition states: OTA is the sum of Drive Input

Edge Placement, Compare Output Edge Placement, and

Drive Input to Compare Output Accuracy. Level 2

analysis will collect data for the first two error

components. The Level 2 parameter not achievable is

Drive Input to Compare Output Accuracy. Level 1 will

determine that value.

12.2.5.1 The Drive Input to Compare Output Accuracy

by definition is the difference between the average of

min & max drive input delay timing and the average of

min & max compare output delay timing. Values for

those components are in the Level 2 data, but because

there is no common reference point for these two

components when the data is taken, their difference

cannot be established from the data at-hand.

12.2.5.2 In summary Level 2 analysis is capable of

independently determining and isolating drive input

timing error and compare output timing error. But,

Level 2 drive input to compare output-timing error can

not be established. Analysis done in Level 1 is required

SEMI G80-0200 © SEMI 200013

to establish Drive Input to Compare Output timing

error. Reference Figure 6.

12.2.6 As noted, Level 1 analysis does establish drive

input to compare output-timing error. But, Level 1

cannot independently determine and isolate drive input

timing error from compare output timing error, as was

accomplished in Level 2. What this means is if the

minimum to maximum drive input to compare output

timing error is established as 1ns (Level 1), the method

cannot create a break down such that so much of that

1ns is input error, with the remaining part of that 1ns

being the output error.

12.2.7 Table 2 data also contains other valuable

components of ATE error that will assist in establishing

ATE timing integrity. Tests that establish the various

components of Input Z Timing error, Multiple Period

Tests for on the fly timing, and for systems with a High

Speed Clock function tests to determine various delay,

jitter and time variation errors.

12.3 A brief word on Drive Input to Compare Output

Timing Accuracy will be made. Drive Input to

Compare Output Timing can be described in different

ways. It is easy to think of this parameter, per the

definition of this aspect of OTA (reference Figure 6), as

simply the relative time difference (skew) between

drive input delay timing (see SEMI G79) and compare

output delay timing (see SEMI G79), for a particular

machine.

But this parameter, once established, is not

necessarily constant. For example, this parameter can

change from one calibration of a machine at a particular

time, to something different, as a result of a subsequent

calibration of that same machine. As well, Drive Input

to Compare Output error can also be considered as a

machine to machine accuracy parameter, not

necessarily having the same value between any two

machines of the same kind.

12.3.1 Thus, on each machine and at different points

in time for the same machine the Drive Input to

Compare Output Timing skew can be uniquely different

per machine. That difference being influenced by the

various machine anomalies that contribute to machine

error including the not so perfect results of a periodic

edge calibration.

12.3.2 In the general case drive input to compare

output as shown in Figure 6 should be thought of in the

context of drive/compare edges having time variance

across multiple machines or as representing edges for

the same machine but having variance across multiple

time intervals associated with different calibrations.

16 Both drive input delay timing and compare output delay timing

values taken at center of spread. By definition center of spread is the

average of min & max: (minerr + maxerr)/2.

12.3.3 Examination of the OTA definition in the

context of Figure 6, that being the general case and not

a single point timing evaluation, reveals that the overall

timing accuracy time value is the time line indicated by

“A” and the time line indicated by “B”. In a single

point AC timing evaluation, OTA is determined as a

distribution of edges associated with time line “A” or

time line “B”, depending upon the relationship between

the drive edge values and compare edge values (see

SEMI G79) at that point in time.

13 Precision, Accuracy, and Precautions

13.1 Precision and Accuracy — Tolerances called-out

in the various steps of this procedure are consistent with

the required supplemental equipment specifications

called for in this Test Procedure.

13.2 Precautions — A precaution is advised when

executing this procedure to the letter. Unreliable

execution or failures may occur as a result of ATE

specification tradeoff that typically exists between

minimum pulse width and drive signal amplitude. This

can be especially true when operation is in conjunction

with complex formats such as SBC. This condition is a

result of specification limitations inherent in the system

under evaluation. Be advised that failure conditions

can occur for systems with inadequate minimum pulse

width and/or inadequate comparator bandwidth

characteristics operating this procedure at high

frequencies with complex formats.

13.3 It is necessary to note that data in Table 1 for any

particular test represents minimum and maximum

values taken for all conditions specified for each test.

Examples of these conditions are parameters such as

frequency, formats, and different voltages. Thus the

precaution lies in how the user interprets the minimum

to maximum deltas. As an example, a minimum value

can occur at a lower frequency whereas a maximum

value for that test may occur at a higher (different)

frequency. Be aware, deltas under broad conditions

may be greater than deltas for a focused condition.

This specification is defined to provide results for the

broad case.

13.4 When entering your analysis results to Table 2

Single Point Overall Timing Accuracy (OTA), be

advised that the Single Point OTA Result is represented

only as indicated in Table 2, the sum of Drive Input to

Compare Output Timing, Drive Input Timing Delay

Error, and Compare Output Time Delay Error. This

appears to deviate from the absolute definition of OTA

in that Drive Input Transition and Drive Input Timing

Cycle Jitter are not included. The method does not lend

itself to making Drive Input Timing Delay Error

measurements that exclude these two components. Per

this method when the Drive Input Timing Delay Error

measurements are made they include these two

parameters. Thus, because of the measurement if

included per the definition, they would be double

counted.

13.5 The OTA definition used in this method does not

include reference parameters shown in Table 2 such as

Drive Input Z Timing Error, Extended Delay, Multiple

Period (timing on the fly), and High Speed Clock

measurements. These are strictly reference timing

parameters. This method is not defined such that they

are to be included as part of OTA. Thus the user is

advised not to sum any of those items as part of the

OTA value entered into Table 2.

13.6 Table 2 is labeled Single Point Overall Timing

Accuracy (OTA) Results. The term “single point” is

used as a reminder for the user of this document that

one execution of this method on a particular ATE

system does not in itself constitute an overall timing

accuracy conclusion for that system. It is simply a

sample of the ATE's performance at some point in time.

A true assessment of an ATE's performance for overall

timing accuracy requires a comprehensive analysis

involving data collection over an extended period of

time that goes well beyond what this method provides

in one pass.

13.7 In general, regarding these pre cautions, the user

is free to adjust the procedure and data collection

according to conditions consistent with the desired

objective. Regardless, if the procedure is performed

under anything other than full-up broad conditions, the

results must be identified as a subset or partial

interoperation of a single point overall timing accuracy

assessment.

14 Related Documents

None.