MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第102页

MIL-STD-883F METHOD 1016.1 18 June 2004 4 3.6 Test resul ts anal ysis . Fail ure analys is of the acc eler ated tes t res ults is nec ess ary to s eparate t he failur es int o temperat ure and nontemper ature dependent c…

MIL-STD-883F

METHOD 1016.1

18 June 2004

3.4.1 Test temperatures

. Unless otherwise specified, test temperatures shall be selected in the range of 200°C to 300°C.

The specified test temperature is the minimum actual ambient temperature to which all devices in the working area of the

chamber shall be exposed. This shall be assured by making whatever adjustments are necessary in the chamber profile,

loading, location of control or monitoring instruments, and the flow of air or other chamber atmosphere. Therefore,

calibration shall be accomplished on the chamber in a fully loaded, unpowered configuration, and the indicator sensor

located at, or adjusted to reflect the coldest point in the working area. For the initial failure rate determination test, three

temperatures shall be selected. A minimum of 25°C separation shall be maintained between the adjacent test temperatures

selected. All other periodic life tests shall be conducted with two temperatures and a minimum of 50°C separation.

3.4.2 Bias circuit selection

. To properly select the accelerated test conditions, it is recommended that an adequate

sample of devices be exposed to the intended high temperature while measuring voltage(s) and current(s) at each device

terminal to assure that the applied electrical stresses do not induce damage. Therefore, prior to performing microcircuit life

tests, test circuit, thermal resistance (where significant), and step-stress evaluations should be performed over the test

ranges, usually 200°C to 300°C. Steps of 25°C for 24 hours minimum duration (all steps of equal duration with a tolerance

of no greater than ±5 percent), each followed by proper electrical measurements, shall be used for step-stress tests.

Optimum test conditions are those that provide maximum voltage at high thermal stress to the most failure-prone junctions

or sites, but maintain the device current at a controlled low level. Excessive device current may lead to thermal runaway

(and ultimately device destruction). Current-limiting resistors shall be employed.

The applied voltage at any or all terminal(s) shall be equal to the maximum rated voltage at 125°C. If necessary, only with

the specific approval of the qualifying activity, the applied voltage at any or all terminals(s) may be reduced to not less than

50 percent of the specified value(s) when it is demonstrated that excessive current flow or power dissipation would result

from operation at the specified voltage(s). If the voltage(s) is so reduced, the life testing time shall be determined in

accordance with the formula given in 3.5.6 of method 1005.

3.5 Life test ground rules

. As an aid to selecting the proper test conditions for an effective microcircuit accelerated life or

screening test, the following rules have been formulated:

a. Apply maximum rated voltage (except as provided in 3.4.2) to the most failure prone microcircuit sites or junctions

identified during step-stress evaluation.

b. Apply electrical bias to the maximum number of junctions.

c. In each MOS or CMOS device, apply bias to different gate oxides so that both positive and negative voltages are

present.

d. Control device currents to avoid thermal runaway and excessive electromigration failures.

e. Employ current-limiting resistors in series with each device to ensure the application of electrical stress to all

nonfailed devices on test.

f. Select a value of each current-limiting resistor large enough to prevent massive device damage in the event of

failure, but small enough to minimize variations in applied voltage due to current fluctuations.

g. Avoid conditions that exceed design or material limitations such as solder melting points.

h. Avoid conditions that unduly accelerate nontypical field condition failure-mechanisms.

i. Employ overvoltage protection circuitry.

The determination of test conditions that conform to the established ground rules involves three basic steps: (1) evaluation

of candidate bias circuits at accelerated test temperatures, (2) device thermal characterization, and (3) the performance of

step-stress tests.

MIL-STD-883F

METHOD 1016.1

18 June 2004

3.6 Test results analysis. Failure analysis of the accelerated test results is necessary to separate the failures into

temperature and nontemperature dependent categories. The nontemperature dependent failures should be removed from

the test data prior to life distribution analysis. All failures shall be reported together with the analysis results and rationale for

deletion of those identified as nontemperature dependent.

3.6.1 Life distribution analysis

. The effectiveness of the test result analysis can be enhanced by diligent failure analysis

of each test failure. Failures should be grouped by similarity of failure mechanisms, that is, surface related, metal migration,

intermetallic formation, etc. The time-to-failure history of each failure in a group should be recorded. This includes the

individual failure times and the associated calculated cumulative percent failures. To facilitate estimating the distribution

parameters from small-sample life tests, the data is plotted as a cumulative distribution. Since semiconductor life

distributions have been shown to follow a lognormal distribution, graph paper similar to figure 1016-1 is required for data

analysis. The lognormal distribution will appear as a straight line on this paper. The expected bimodal distribution of "freak"

and "main" populations in a combined form normally appears as an s-shaped plot. The distribution parameters necessary

for data analysis, median life and sigma (σ) can be calculated as:

≈ ln

time of failure

50%

16%

Separate analysis of the individual "freak" and "main" populations should be performed and "goodness of fit" tests applied to

test the apparent distribution(s).

3.6.2 Life acceleration analysis

. Life/reliability characterization requires the establishing of failure distributions for several

temperature stress levels at the same rated voltage condition. These failure distributions must represent a common failure

mechanism. Using a specially prepared graph paper for Arrhenius Reaction Rate Analysis as shown in figure 1016-2, the

median life times for the "freak" and "main" populations can be plotted to determine equivalent life-times at the desired use

temperatures.

3.6.3 Failure rate calculations

. Semiconductor failures are lognormally distributed. Therefore, the failure rate will vary

with time. Semiconductor failure rates at any given time can be calculated using figure 1016-3 which is a normalized

presentation of the mathematical calculations for the instantaneous failure rate from a lognormal distribution.

4. SUMMARY

. The following details shall be as specified in the applicable acquisition document:

a. Test temperature(s) and whether ambient or case.

b. Test mounting if other than normal (see 3).

c. Endpoint measurements (see 3.2).

d. Intermediate measurements (see 3.2).

e. Criteria for failure for endpoint and intermediate measurements (see 3.2), if other than device specification limits.

f. Test sample (see 3.3).

g. Requirements for inputs, outputs, biases, test circuit, and power dissipation, as applicable (see 3.4).

MIL-STD-883F

METHOD 1016.1

18 June 2004

h. Requirements for data analysis, including:

(1) Failure analysis results.

(2) Data calculations:

(a) Log normal by temperature.

(b) Reaction rate relationships