MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第123页

MIL-STD-883F METHOD 1019.6 7 March 2003 7 3.12.2 Ac celer ated anneali ng test procedur e . If the devic e passes the tes ts in 3.1 thr ough 3.10 or i f it passes 3.11 ( if that procedur e is us ed) to t he total ionizi …

MIL-STD-883F

METHOD 1019.6

7 March 2003

b. The test will be carried out in such a fashion that the case of the device under test will have a temperature within

the range 24°C ± 6°C.

c. Where possible, the room temperature anneal should continue for a length of time great enough to allow device

parameters that have exceeded their pre-irradiation specification to return to within specification or post-irradiation-

parametric limit (PIPL) as established by the manufacturer. However, the time of the room temperature anneal

shall not exceed t

max

, where

spec

max

spec

is the total ionizing dose specification for the part and R

max

is the maximum dose rate for the intended use.

d. Test the device under test for electrical performance as specified in 3.7 and 3.8. If the device under test passes

electrical performance tests following the extended room temperature anneal, this shall be considered acceptable

performance for a very low dose rate environment in spite of having previously failed the post-irradiation and

electrical tests of 3.1 through 3.10.

3.12 MOS accelerated annealing test

. The accelerated annealing test provides an estimate of worst-case degradation of

MOS microcircuits in low dose rate environments. The procedure involves heating the device following irradiation at

specified temperature, time and bias conditions. An accelerated annealing test (see 3.12.2) shall be performed for cases

where time dependent effects (TDE) can cause a device to degrade significantly or fail. Only standard testing shall be

performed as specified in 3.1 through 3.10 for cases where TDE are known not to cause significant device degradation or

failure (see 3.12.1) or where they do not need to be considered, as specified in 3.12.1.

3.12.1 Need to perform accelerated annealing test

. The parties to the test shall take appropriate steps to determine

whether accelerated annealing testing is required. The following criteria shall be used:

a. The tests called out in 3.12.2 shall be performed for any device or circuit type that contains MOS circuit elements

(i.e., transistors or capacitors).

b. TDE tests may be omitted if:

1. circuits are known not to contain MOS elements by design, or

2. the ionizing dose in the application, if known, is below 5 krad(Si), or

3. the lifetime of the device from the onset of the irradiation in the intended application, if known, is short

compared with TDE times, or

4. the test is carried out at the dose rate of the intended application, or

5. the device type or IC technology has been demonstrated via characterization testing not to exhibit TDE

changes in device parameters greater than experimental error (or greater than an otherwise specified upper

limit) and the variables that affect TDE response are demonstrated to be under control for the specific vendor

processes.

At a minimum, the characterization testing in (5) shall include an assessment of TDE on propagation delay,

output drive, and minimum operating voltage parameters. Continuing process control of variables affecting

TDE may be demonstrated through lot sample tests of the radiation hardness of MOS test structures.

c. This document provides no guidance on the need to perform accelerated annealing tests on technologies that do

not include MOS circuit elements.

MIL-STD-883F

METHOD 1019.6

7 March 2003

3.12.2 Accelerated annealing test procedure

. If the device passes the tests in 3.1 through 3.10 or if it passes 3.11 (if that

procedure is used) to the total ionizing dose level specified in the test plan or device specification or drawing and the

exclusions of 3.12.1 do not apply, the accelerated annealing test shall be conducted as follows:

a. Overtest

1. Irradiate each test device to an additional 0.5-times the specified dose using the standard test conditions (3.1

through 3.10). Note that no electrical testing is required at this time.

2. The additional 0.5-times irradiation in 3.12.2.a.1may be omitted if it has been demonstrated via

characterization testing that:

a. none of the circuit propagation delay, output drive, and minimum operating voltage parameters recover

toward their pre-irradiation value greater than experimental accelerated annealing test of 3.12.2.b, and

b. the irradiation biases chosen for irradiation and accelerated annealing tests are worst-case for the

response of these parameters during accelerated annealing.

The characterization testing to establish worst-case irradiation and annealing biases shall be performed at the

specified level. The testing shall at a minimum include separate exposures under static and dynamic

irradiation bias, each followed by worst-case static bias during accelerated annealing according to 3.12.2.b.

b. Accelerated annealing

. Heat each device under worst-case static bias conditions in an environmental chamber

according to one of the following conditions:

1. At 100°C ±5°C for 168 ±12 hours, or

2. At an alternate temperature and time that has been demonstrated via characterization testing to cause equal

or greater change in the parameter(s) of interest, e.g., propagation delay, output drive, and minimum

operating voltage, in each test device as that caused by 3.12.2.b.1, or

3. At an alternate temperature and time which will cause trapped hole annealing of >60% and interface state

annealing of <10% as determined via characterization testing of NMOS test transistors from the same

process. It shall be demonstrated that the radiation response of test transistors represent that of the device

under test.

c. Electrical testing.

Following the accelerated annealing, the electrical test measurements shall be performed as

specified in 3.8 and 3.9.

MIL-STD-883F

METHOD 1019.6

7 March 2003

3.13 Test procedure for Bipolar and BiCMOS linear or mixed signal circuits with agreed to dose rates of less than 50

rad(Si)/s. Many bipolar linear parts exhibit ELDRS, which cannot be simulated with a room temperature 50-300 rad(Si)/s

irradiation plus elevated temperature anneal, such as that used for MOS parts (see ASTM-F1892 for more technical details).

Parts that exhibit ELDRS shall be tested either at the agreed to dose rate, at a prescribed low dose rate to an overtest

radiation level, or with an elevated temperature irradiation test that includes a parameter delta design margin.

Need to perform low dose rate testing

a. The low dose rate tests described in 3.13 may be omitted if:

1. circuits are known not to contain bipolar transistors by design, or

2. circuits are known not to contain any linear circuit functions by design.

3. the device type and IC technology have been demonstrated via characterization testing not to exhibit

ELDRS in device parameters greater than experimental error (or greater than an otherwise specified

upper limit) and the variables that affect ELDRS response are demonstrated to be under control for the

specific vendor processes.

3.13.1 Low dose rate or elevated temperature irradiation test for bipolar or BiCMOS linear or mixed-signal circuits

. All

circuits that do not meet the exception of 3.13.a shall be tested using one of the following test conditions.

Note: The test procedures in paragraphs b. and c. below represent a compromise between the desire for a conservative,

worst-case test and the constraints of test cost, schedule and facilities. For this reason, the test procedures may

result in a non-conservative test for some kinds of circuits.

a. Test at the agreed to dose rate

. Irradiate each test device at the dose rate described in 3.6.3 Condition C using

the standard test conditions (3.1 through 3.10).

b. Test at a prescribed low dose rate

. Irradiate each test device at the close rate described in 3.6.4 Condition D

using the standard test conditions (3.1 through 3.10) with the following additional requirements:

1. If the dose rate is <

10 mrad(Si)/s, an overtest factor of 1.5 shall be applied to the radiation test level, i.e.

the part must pass at a radiation level of 1.5 times the specification dose to be acceptable.

2. If the dose rate is greater than 10 mrad(Si)/s, an overtest factor of 2.0 shall be applied to the radiation

test level, i.e. the part must pass at a radiation level of 2.0 times the specification dose to be acceptable.

c. Test at an elevated temperature

. Irradiate each test device at the dose rate described in 3.6.5 Condition E using

the standard test conditions (3.1 through 3.10) with the following additional requirements:

1. The irradiation temperature shall be 100°C ± 5°C using an irradiation test chamber as described in

paragraph 2.8. Every effort shall be made to minimize the time at temperature.

2. The elevated temperature irradiation test shall only be used for parts with a specification dose of 50

krad(Si) or less.

3. All pre and post irradiation electrical measurements shall be made at a temperature of 24°C ±6°C.

4. A parameter design margin of 3 shall be applied at the specification dose to all critical electrical

parameters in the following manner. The change in each electrical parameter shall be calculated for

each sample at the specification dose. This change in the parameter shall be multiplied by 3 and added

(or subtracted) to the post irradiation parameter value for each sample. This value shall be compared to

the allowable degraded value of the parameter to determine whether the sample passes or fails the test.