MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第172页

MIL-STD-883F METHOD 1032.1 29 May 1987 4 4. SUMMARY . The fol lowing detai ls s hall be s pecif ied. a. Devic e type and quanti ty to be tes ted. b. Test cir cuit to be used. c. Devi ce output pins t o be monitored. d. A…

MIL-STD-883F

METHOD 1032.1

29 May 1987

f. The flux at the surface of the die will be determined when the die coat is in place; this is designated as the

modified package flux.

NOTE: The modified package flux should be the sum of the flux from the die and die-coat material only.

g. The die coat should be removed, assuring that no damage to the die has occurred and the source placed as

described in step b.

h. The tests performed in step 3.c must be repeated with this configuration, and the new SER will be designated

SER

i. Recorded for each test performed will be the following:

(1) Total number of errors recorded during each test.

(2) Time to accumulate the errors.

(3) SER (SER

), calculated from the following formulas:

ASER

= Total number of errors/test time

SER

= ASER

x (Modified package flux/source flux)

j. The SER for the corresponding tests will be summed and reported as the rate of failure for this DUT, using the

following formula:

SER = SER

+ SER

NOTE: The order of the steps above can be reversed to enable testing before the die coat is applied and then after it has

been applied, if desired.

3.1 Test plan

. A test plan will be devised which will include determination of the worst case operating environment of the

DUT to determine the worst case SER, incorporating the steps outlined above. The data patterns used will ensure that each

cell and path, or both, is tested for both the logic zero and logic one states. The device will be continuously monitored and

refreshed and the data errors counted. This test will be required for each new device type or design revisions. The source

value and exposure time will be sufficient to obtain a significant number of soft error failures.

NOTE: If a data-retention or a reduced supply mode is a valid operating point for the DUT, this condition must also be

tested for its SER.

3.1.1 The test equipment program

. The test equipment program will be devised to cycle and refresh the stored data or

cycled pattern continually, recording the number of errors.

3.1.2 Test conditions

. Testing shall be performed at three separate cycle rates and at minimum and maximum voltages.

Unless otherwise specified, the following cycle timing will be used: The minimum and the maximum specified cycle timing

and the midpoint between the minimum and maximum specified cycle timing.

NOTE: If the device is a static or dynamic random access memory device, the device will be tested under both read and

write operations.

3.2 Report

. As a minimum, the report will include device identification, test date, test operator, test facility (if applicable),

radiation source, test cycle times and voltages, data analysis, and equipment used in the test.

MIL-STD-883F

METHOD 1032.1

29 May 1987

4. SUMMARY

. The following details shall be specified.

a. Device type and quantity to be tested.

b. Test circuit to be used.

c. Device output pins to be monitored.

d. Alpha source used if other than specified herein.

e. Alpha source Curie level.

f. Package flux measurement techniques.

g. Test equipment to be used.

h. Procedures for proper handling of radioactive materials.

MIL-STD-883F

METHOD 1033

29 May 1977

METHOD 1033

ENDURANCE LIFE

1. PURPOSE

. Endurance life is performed in order to demonstrate the quality and reliability of nonvolatile memory

devices subjected to repeated write/erase cycles. This method may also be used in a screening sequence or as a

preconditioning treatment prior to conducting other tests. It may be desirable to make end point, and where applicable,

intermediate measurements on a serialized device basis or on the basis of a histogram distribution by total sample in order

to increase the sensitivity of the test to parameter degradation or the progression of specific failure mechanism with cycles,

time, or temperature.

1.1 Terms and definitions

1.1.1 Endurance

. The number of write/erase cycles a device can tolerate before failing to perform to specification.

1.1.2 Write/erase cycle

. The act of changing the data from original to opposite to original in all bits of a memory device.

This may be done for all bits in parallel or serial, e.g., block, byte, or bit.

1.1.3 Data retention screen

. The unbiased baking at high temperature to accelerate the loss of charge from the storage

node.

2. APPARATUS

. The apparatus required for this test shall consist of equipment capable of write/erase cycling the

devices, a controlled temperature chamber for performing a data retention bake, and suitable electrical test equipment to

make the specified interim and end point measurements.

3. PROCEDURE

. The devices shall be write/erase cycled (all bits) for specified maximum number of cycles, followed by

electrical test, the specified data retention bake and electrical test. Interim pull points shall use the same sequence of cycle,

electrical test, data retention bake, and electrical test.

3.1 Test condition

. The case temperature, cycle time, data retention bake, and electrical test temperatures and

conditions will be specified in the applicable device specification or drawing (see 4).

3.2 Failure criteria

. No device is acceptable that exhibits:

a. Inability to write or erase across the temperature range.

b. Inability to retain data.

c. Inability to read at specified timing conditions, across the temperature and supply voltage range.

d. Inability to be write/erase cycled a minimum number of times n.