MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第313页

MIL-STD-883F METHOD 2018.4 18 June 2004 1 METHOD 2018.4 SCANNING ELECTRON MICROSCOPE (SEM) INSPECTIONS 1. PURPOSE . This method provi des a means of judging the qual ity and ac ceptabi lity of device i nterc onnect metal…

MIL-STD-883F

METHOD 2017.8

18 June 2004

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MIL-STD-883F

METHOD 2018.4

18 June 2004

METHOD 2018.4

SCANNING ELECTRON MICROSCOPE (SEM) INSPECTIONS

1. PURPOSE

. This method provides a means of judging the quality and acceptability of device interconnect metallization

on non-planar oxide integrated circuit wafers or dice. SEM inspection is not required on planar oxide interconnect

technology such as chemical mechanical polish (CMP) processes. It addresses the specific metallization defects that are

batch process orientated and which can best be identified utilizing this method. Conversely, this method should not be used

as a test method for workmanship and other type defects best identified using method 2010.

Samples submitted to SEM shall not be shipped as functional devices unless it has been shown that the device structure, in

combination with the equipment operating conditions, is nondestructive.

1.1 Definitions

1.1.1 Barrier adhesion metal

. The lower layer of multi-layer metal system deposited to provide a sound mechanical bond

to silicon/silicon oxide surfaces or to provide a diffusion barrier of a metal into an undesired area such as aluminum into a

contact window.

1.1.2 Cross-sectional plane

. An imaginary plane drawn perpendicular to current flow and which spans the entire width of

the metallization stripe as illustrated in figure 2018-1. Metallization stripes over topographical variations (e.g., passivation

steps, cross-overs, bird's head), which are nonperpendicular to current flow, are projected onto cross-sectional planes for

purposes of calculating cross-sectional area reductions.

1.1.3 Destructive SEM

. The use of specific equipment parameters and techniques that result in unacceptable levels of

radiation damage or contamination of the inspected semiconductor structure.

1.1.4 Directional edge

. A directional edge (see figure 2018-2) is typically the edge(s) of a rectangular contact window

over which metallization may be deposited for the purpose of carrying current into, through, or out of the contact window for

device operation. It should be noted that contact geometry, site of concern, or both may vary and if so, the directional edge

concept should be modified accordingly.

1.1.5 General metallization (conductors)

. The metallization at all locations including metallization (stripes) in the actual

contact window regions with the exception being at areas of topographical variation (e.g., passivation steps, bird's head,

cross-overs).

1.1.6 Glassivation

. Glassivation is the top layer(s) of transparent insulating material that covers the active circuit area

(including metallization), except bonding pads and beam leads.

1.1.7 Interconnection

. The metal deposited into a via to provide an electrical conduction path between isolated metal

layers.

1.1.8 Major current-carrying directional edge

. The directional edge(s) which is designed to provide a path for the flow of

current into, through, or out of a contact window or other area(s) of concern (see figure 2018-2).

1.1.9 Multi-layer metallization (conductors)

. Two or more layers of metal used for electrical conduction that are not

isolated from each other by a grown or deposited insulating material. The term "underlying metal" shall refer to any layer

below the top layer of metal.

1.1.10 Multi-level metallization (conductors)

. A single layer or a multi-layer of metal shall represent a single level of

metallization. A combination of such levels, isolated from each other by a grown or deposited layer of insulating material,

shall comprise the multi-level metallization interconnection system. The use of vias to selectively connect portions of such

level combinations through the isolation shall not effect this definition.

MIL-STD-883F

METHOD 2018.4

18 June 2004

1.1.11 Nondestructive SEM. The use of specific equipment parameters and techniques that result in negligible radiation

damage, contamination, or both of the inspected semiconductor structure (see 3.10 and 3.11).

1.1.12 Passivation

. The silicon oxide, nitride or other insulating material that is grown or deposited on the die prior to

metallization.

1.1.13 Passivation steps

. The vertical or sloped surface resulting from topographical variations of the wafer surface (e.g.,

contact windows, diffusion cuts, vias, etc.).

1.1.14 Via

. The opening in the insulating layer to provide a means for deposition of metal to interconnect layers of metal.

1.1.15 Wafer lot

. A wafer lot consists of microcircuit wafers formed into a lot at the start of wafer fabrication for

homogeneous processing as a group and assigned a unique identifier or code to provide traceability and maintain lot

integrity throughout the fabrication process.

2. APPARATUS

. The apparatus for this inspection shall be a scanning electron microscope (SEM) having resolution of

250Å or less as measured on the photograph at use conditions and a variable magnification of 1,000X to 20,000X or greater.

The apparatus shall be such that the specimen can be tilted to a viewing angle (see figure 2018-3) between 0° and 85°, and

can be rotated through 360°.

2.1 Calibration

. The magnification shall be within ±10 percent of the nominal value when compared with National Institute

of Standards and Technology standard 484 or an equivalent at the magnification(s) used for inspection. The resolution shall

be 250Å or less as verified with National Institute of Standards and Technology standard SRM-2069 or equivalent.

Magnification and resolution verification shall be performed on a frequency defined by the manufacturer based on statistical

data for his SEM equipment.

2.2 Operating personnel

. Personnel who perform SEM inspection shall have received adequate training in equipment

operation and interpretation of the images and resulting photographs prior to attempting certification for metallization

inspection. Procedures for certification of SEM operators for metallization inspection shall be documented and made

available for review upon request to the qualifying activity, or when applicable, a designated representative of the acquiring

activity. This shall include provisions for recertification procedures once a year as a minimum.

Operator certifications and recertifications shall be documented and made available for review upon request to the qualifying

activity, or when applicable, a designated representative of the acquiring activity.

2.3 Procedures

. There shall be written procedures for metallization inspection. These procedures shall be documented

and made available for review upon request to the qualifying activity, or when applicable, a designated representative of the

acquiring activity.

3. PROCEDURE

3.1 Sample selection

. Statistical sampling techniques are not practical here because of the large sample size that would

be required. The wafer sampling requirements defined in table I, taken in conjunction with specific dice locations within the

sampled wafers, minimize test sample size while maintaining confidence in test integrity. These dice are in typical or worst

case positions for the metallization configuration.

Note: When die or packaged parts are to be evaluated for wafer lot acceptance and the requirements for wafer selection per

Table I cannot be met, the following sample size shall be utilized:

a. If the die/packaged part is from a known homogeneous wafer lot (traceability specific to the wafer or wafer lot and

objective evidence is available for verification), then the sample size shall be 8 devices randomly selected from the

population.

b. If the die/packaged part is from a non-homogeneous wafer lot (traceability is unknown or no objective evidence is

available for verification), then the sample size shall be 22 devices randomly selected from the population.

Die area submitted for SEM evaluation shall not have been or be located immediately adjacent to the wafers edge, and they

shall be sufficiently free of smearing, so that the required inspection can be conducted in an area of undisturbed

metallization. Acceptance of the interconnect metallization shall be based on examination of selected die area, using either

a single wafer acceptance basis or a wafer lot acceptance basis.