MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第320页

MIL-STD-883F METHOD 2018.4 18 June 2004 8 3.7.2. 1.1 Conditi on 1 . It is det ermined t hat the dir ecti onal edge prof ile fr om which met al is absent does not oc cur i n the major cur rent- carr ying dir ecti onal edg…

MIL-STD-883F

METHOD 2018.4

18 June 2004

3.6 Acceptance requirements.

3.6.1 Single wafer acceptance basis

. The metallization on a single wafer shall be judged acceptable only if all the

sampled areas or dice from that wafer are acceptable.

3.6.2 Wafer lot acceptance basis

. An entire wafer lot shall be judged acceptable only when all the sampled areas or dice

from all sample wafers are acceptable. If a wafer lot is rejected in accordance with this paragraph each wafer from that

wafer lot may be individually examined; acceptance shall then be in accordance with 3.6.1.

3.7 Accept/reject criteria

. Rejection of dice shall be based on batch process defects and not random defects such as

scratches, smeared metallization, tooling marks, etc. In the event that the presence of such random defects obscures the

detailed features being examined, an additional adjacent sample shall be inspected. Illustrations of typical defects are

shown in figures 2018-6 through 2018-22.

3.7.1 General metallization

. Any evidence of poor metallization adhesion shall be unacceptable. Any defects (see figure

2018-18 and 2018-20), such as voids, cracks, separations, depressions, notches, or tunnels, which singly or in combination

reduce the cross-sectional area of the general metallization stripe by more than 50 percent shall be unacceptable. Two

specific cases of general metallization are specified below:

3.7.1.1 Conductor stripes

. In the examination of the other metal layers for the specific case of conductor stripes

(exclusive of the contact window area), a defect consuming 100 percent of the thickness of the barrier/adhesion stripe shall

be acceptable provided that the defect does not extend more than 50 percent across the width of the metallization stripe

(see figure 2018-22).

3.7.1.2 Barrier layers in contact window areas

. No defects of any kind in a barrier layer which would bring the overlying

metal layer in contact with the semiconductor material surface shall be permitted.

3.7.1.3 Overlying adhesion layers

. For the metal layer(s) above the principal conducting layer, a defect consuming 100

percent of the thickness of the adhesion stripe shall be acceptable provided that the defect does not extend more than 50

percent across the width of the metallization stripe.

3.7.2 Passivation steps

. Metallization over a passivation step shall be unacceptable if any combination of defects (see

figure 2018-23) or thinning of the metal reduces the cross-sectional area of the metallization stripe along any cross-sectional

plane in a major current-carrying direction to less than 50 percent of the cross-sectional area of the stripe. A minimum of 20

percent total metallization coverage (barrier metal inclusive, see figure 2018-24) in the primary current carrying direction will

be allowed for metallization over a passivation step when the structure involved is a circular or multisided via or contact

structure and there is sufficient wrap-around metal (>10 percent of incoming metal line width) to allow for current flow to all

sides of the via or contact. The metallization must meet the current density requirements of MIL-PRF-38535. In cases

where an absence of visible edge or a smooth transition or taper clearly reveals effective coverage, a cross-section will be

performed to verify metal coverage.

3.7.2.1 Nonrejectable cross-sectional area

. In the event that the metallization cross-sectional area at a particular directional

edge profile is less than as allowed in 3.7.2. This shall not be cause for rejection if the following two conditions occur:

MIL-STD-883F

METHOD 2018.4

18 June 2004

3.7.2.1.1 Condition 1. It is determined that the directional edge profile from which metal is absent does not occur in the

major current-carrying directional edge. Such determination shall be made either by scanning all passivation steps of this

type on the remainder of the die, or by the examination of a topographical map supplied by the manufacturer which shows

the metal interconnect pattern.

3.7.2.1.2 Condition 2

. Acceptance shall be on a single wafer basis only.

3.7.2.2 Nonrejectable, noncovered directional edge

. For passivation steps to be acceptable, all directional edges shall be

covered with metallization and be acceptable to the requirements of 3.7.2.1, unless by design. In the event that a directional

edge profile of a particular type of passivation step is not covered with metallization, this shall not be cause for rejection if

the following two conditions occur:

3.7.2.2.1 Condition 1

. It is determined that the directional edge profile from which metal is absent does not occur in the

major current-carrying directional edge. Such determination shall be made either by scanning all passivation steps of this

type on the remainder of the die, or by the examination of a topographical map supplied by the manufacturer which shows

the metal interconnect pattern.

3.7.2.2.2 Condition 2

. None of the other specimens from the sampled wafers representing the lot exhibit a directional

edge profile from which metal is absent in the major current-carrying directional edge.

NOTE: If both 3.7.2.2.1 and 3.7.2.2.2 are satisfied, a wafer lot acceptance basis shall be used. However, if only 3.7.2.2.1 is

satisfied, a single wafer acceptance basis shall be used.

3.7.3 Verification of potential rejects

. At the option of the manufacturer, it shall be permissible to subject the specimen, or

an adjacent sample that exhibits the same reject mode, to a verification test. Given below are some examples of suitable

verification tests:

3.7.3.1 Cross-sectioning

. A passivated sample shall be cleaved or lapped down to bisect the area of concern. The

sample may then be subjected to an etchant that will remove the interconnecting metallization at the inspection surface (i.e.,

approximately perpendicular to the die surface). Specimens may be examined without any special surface coating if surface

charging is not a significant problem and adequate resolution and signal-to-noise levels are obtained. If the specimens are

coated, they shall be coated with a thin vapor-deposited or sputtered film of a suitable conductive material (i.e., 100Å gold).

The coating deposition processes shall be controlled such that no artifacts are introduced by the coating. The sample shall

be prepared (see 3.3) and examined in the SEM for interconnect metallization thickness or percentage coverage at the

passivation step, or any other relevant parameter. Note: This cross-sectioning technique is not conclusive for hairline

microcracks as they are not adequately filled by the passivation material.

3.7.3.1.1 Dimensional errors

. Care must be taken to ensure that the cross-section is close to the center of a contact in

order to avoid dimensional errors due to the rounding of the contact corners.

3.7.3.2 Surface etchback

. The unpassivated sample surface is subjected to a chemical etch which removes the

interconnection metallization from the surface of the die at a known controlled rate. The etching is stopped when the

required metal thickness has been removed. The sample is then prepared (see 3.3) and examined within the SEM for

residual metal at the passivation step/contact window interface. Photographic evidence shall then be taken of the sample(s)

to support the acceptance or rejection of the material.

3.7.3.3 Topographical integration

. A graphical representation of the worst case cross-sectional area is drawn to scale on

appropriate graph paper from comprehensive photographs taken eucentrically about the directional edge. The

cross-sectional area is then graphically integrated. This technique is useful for evaluating metallization with irregular surface

topography.

3.8 Specimen documentation requirements

. A minimum of three photographs for each layer of each level of metallization

inspected per lot shall be taken and retained for a minimum of five years after performance of the inspection. Two

photographs shall be of worst case passivation steps and the third photograph of worst case general metallization. If any

photograph shows an apparent defect within the field of view, another photograph shall be taken to certify the extent of the

apparent defect (see table II).

MIL-STD-883F

METHOD 2018.4

18 June 2004

NOTE: Alternate methods of image storage (e.g., video disk or video tape) shall be acceptable with the prior approval of the

qualifying activity.

3.8.1 Required information

. The following information shall be traceable to each photograph:

a. Date of SEM photograph.

b. Device or circuit identification (type or part number).

c. Area of photographic documentation.

d. Electron beam accelerating voltage.

e. Magnification.

f. Manufacturer.

g. Manufacturer's lot identification number.

h. Record of calculated/measured percentage step coverage.

i. SEM operator or inspector's identification.

j. Viewing angle.

3.9 Disposition of inspected specimens

. SEM samples and contiguous die shall not be shipped as functional devices

unless nondestructive SEM conditions and requirements are met (see 3.10). In order to be considered nondestructive,

suitable life-test data (see 3.11) shall be submitted for approval to the qualifying activity to substantiate the nondestructive

aspects of the test (e.g., radiation hardness degradation-RHD). Additionally, all of the conditions in 3.10 and 3.11 must be

satisfied.

3.10 Nondestructive SEM conditions

. For nondestructive SEM, the following conditions shall apply:

3.10.1 Equipment conditions

a. The accelerating voltage shall be within the 0.5 kV to 2.0 kV range.

b. The absorbed specimen current (as measured with a Faraday cup) shall be less than 500 pA.

c. Total scan time for each test site on the wafer shall not exceed ten minutes.

d. Resolution for metal inspection shall be in accordance with 2 above at the accelerating voltage of 3.10.1a. When

used for other in-line nondestructive SEM evaluations (e.g., photoresist, critical dimension (cd) inspection, etc.) the

resolution shall be sufficient to clearly verify the measurement.

3.10.2 Wafer conditions

a. The wafer lot shall satisfy the thermal stability criteria defined within MIL-STD-883, method 5007, table I.

b. Weekly monitoring of particle counts shall be conducted in the SEM inspection area. The particle count limits shall

be less than or equivalent to the specified wafer fab limits.

c. The wafer shall be clean and free of any surface coating.