MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第398页

MIL-STD-883F METHOD 2028.4 27 July 1990 2 This page i ntenti onally lef t blank

MIL-STD-883F

METHOD 2028.4

27 July 1990

METHOD 2028.4

PIN-GRID PACKAGE DESTRUCTIVE LEAD PULL TEST

1. PURPOSE

. This method provides a test for determining the integrity of pin-grid type package leads by measuring the

capability of the package leads to withstand an axial force.

2. APPARATUS

. The apparatus for this test shall consist of suitable equipment for supplying the specified stress to the

package lead. A calibrated measurement and indication of the applied stress in grams-force (gf) shall be provided by

equipment capable of measuring stresses up to twice the specified minimum limit value, with an accuracy of ±5 percent or

±0.25 kgf, whichever is greater.

3. PROCEDURE

. The stress shall be applied to the leads to be tested randomly selected from a minimum of 3 devices

prior to start of the test. Tension only shall be applied, without shock, to each lead to be tested in a direction parallel to the

axis of the lead. The tension shall be increased until the minimum acceptable pull strength is reached or upon separation of

the lead from the braze pad. The tension shall be applied as close to the end of the lead as possible.

3.1 Failure criteria

. The minimum acceptable lead pull strength shall be 1.70 X 10

grams-force per square inch of

cross-sectional lead area (e.g., the minimum pull strength of a lead with an average cross-sectional area of 2.5 x 10

-4

will

be 4.3 kgf.)

4. SUMMARY

. The following details shall be specified in the applicable acquisition document:

a. Number and selection of leads, if different from above.

b. Measured lead pull strength and minimum required pull strength, if different from above.

MIL-STD-883F

METHOD 2028.4

27 July 1990

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MIL-STD-883F

METHOD 2029

29 May 1987

METHOD 2029

CERAMIC CHIP CARRIER BOND STRENGTH (DESTRUCTIVE PUSH TEST)

1. PURPOSE

. The purpose of this test method is to measure strengths of bonds external to leadless microelectronic

packages (e.g., solder bonds from chip carrier terminals to substrate or wiring board).

2. APPARATUS

. The apparatus for this test method shall consist of suitable equipment for applying the specified stress

to the device terminals. A calibrated measurement and indication of the applied stress in grams force (gf) shall be provided

by equipment capable of measuring stresses up to twice the specified limit value, with an accuracy of ±5 percent or ±0.25 gf,

whichever is the greater tolerance.

3. PROCEDURE

. The test shall be conducted using the following test procedure. All push tests shall be counted and the

specified sampling, acceptance, and added sample provisions shall be observed, as applicable. A minimum of 4 chip

carriers (or use all chip carriers if 4 are not available) on each of a minimum of 2 completed substrates or wiring boards shall

be used. Where there is any adhesive, encapsulant, or other material under, on, or surrounding the chip carrier such as to

increase the apparent bond strength, the bond strength test shall be performed prior to application.

3.1 Test samples

. When packages are bonded to substrates or wiring boards other than those in completed devices, the

following conditions shall apply:

a. The sample of packages for this test shall be taken at random from the same chip carrier population as that used in

the completed devices that they are intended to represent.

b. The packages for this test shall be bonded on the same bonding apparatus as the completed devices, during the

time period within which the completed devices are bonded.

c. The test package substrates shall be processed and handled identically with the completed device substrates,

during the same time period within which the completed device substrates are processed.

3.1.1 Sample preparation

. Substrates must be prepared as follows:

a. A roughly circular area comprising 50 percent, +5 percent, -0 percent of the bonded side of each package to be

tested shall be exposed by either end-mill drilling of the test substrate or other suitable means. If it is not possible

to expose the ceramic in this manner, the packages shall be bonded onto test substrates into which the proper

hole(s) and hole size(s) has (have) been manufactured, providing all other conditions of 3.1 have been met.

b. Suitable support must be provided for the test substrate so that there is a minimum of flexure of the substrate

during the test. This support, if necessary, may be provided by bonding the substrate to a rigid metal plate having

a hole pattern matching that of the test substrate.

c. A cylindrical rigid metal test post must be prepared for each hole size, which will be inserted through the support

plate and test substrate holes. The post will be used to transmit the specified stress from the stress-source

equipment to the exposed package surface. The diameter of the post shall be 85 percent (+5 percent, -0 percent)

of the corresponding test hole diameter. The length of the post shall be sufficient to extend 1 inch (+100 percent,

-0 percent) from the open end of the test hole when the post is inserted completely into the hole.

3.2 Testing

. The test shall be performed in the following manner:

a. A single package shall be pushed during each test sequence.

b. A layer of teflon tape in accordance with MIL-T-27730 or equivalent shall be placed between the exposed chip

carrier surface and the test post prior to testing.