MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第488页

MIL-STD-883F METHOD 3004.1 15 November 1974 2 FI GURE 3004-1. Tr ansit ion time meas urements .

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MIL-STD-883F
METHOD 3004.1
15 November 1974
1
METHOD 3004.1
TRANSITION TIME MEASUREMENTS
1. PURPOSE
. This method establishes the means for measuring the output transition times of digital microelectronic
devices, such as TTL, DTL, RTL, ECL, and MOS.
1.1 Definitions
. The following definitions shall apply for the purpose of this method.
1.1.1 Rise time (t
TLH
). The transition time of the output from 10 percent to 90 percent or voltage levels of output voltage
with the specified output changing from the defined LOW level to the defined HIGH level.
1.1.2 Fall time (t
THL
). The transition time of the output from 90 percent to 10 percent or voltage levels of output voltage
with the specified output changing from the defined HIGH level to the defined LOW level.
2 APPARATUS
. Equipment capable of measuring the elapsed time between specified percentage points (normally 10
percent to 90 percent on the positive transition and 90 percent to 10 percent on the negative transition) or voltage levels.
The test chamber shall be capable of maintaining the device under test at any specified temperature.
3. PROCEDURE
. The device shall be stabilized at the specified test temperature. The device under test shall be loaded
as specified in the applicable acquisition document. The load shall meet the requirements specified in method 3002 of this
document. The driving signal shall be applied as specified in method 3001 or the applicable acquisition document.
3.1 Measurement of t
TLH
and t
THL
. Unless otherwise stated, the rise transition time (t
TLH
) shall be measured between the
10 percent and 90 percent points on the positive transition of the output pulse and the fall transition time (t
THL
) shall be
measured between the 90 percent and 10 percent points on the negative transition of the output pulse. The device under
test shall be conditioned according to the applicable acquisition document with nominal bias voltages applied. Figure 3004-1
shows typical transition time measurement.
4. SUMMARY
. The following details shall be specified in the applicable acquisition document:
a. t
TLH
limits.
b. t
THL
limits.
c. Transition time measurement points if other than 10 percent or 90 percent.
d. Parameters of the driving signal.
e. Conditioning voltages (static or dynamic).
f. Load condition.
g. Power supply voltages.
h. Test temperature.
MIL-STD-883F
METHOD 3004.1
15 November 1974
2
FIGURE 3004-1. Transition time measurements
.
MIL-STD-883F
METHOD 3005.1
15 November 1974
1
METHOD 3005.1
POWER SUPPLY CURRENT
1. PURPOSE
. This method establishes the means for measuring power supply currents of digital microelectronic devices
such as TTL, DTL, RTL, ECL, and MOS.
2. APPARATUS
. Equipment capable of applying prescribed voltage to the test circuit power supply terminals and
measuring the resultant currents flowing in these terminals shall be provided. The test chamber shall be capable of
maintaining the device under test at any specified temperature.
3. PROCEDURE
. The device shall be stabilized at the specified test temperature.
3.1 I
CCH
(logic gate). Inputs of the device under test shall be conditioned in such a way as to provide a HIGH level at the
output, the worst case supply voltage(s) shall be applied and the resultant current flow in the supply terminals measured.
3.2 I
CCL
(logic gate). Inputs of the device under test shall be conditioned in such a way as to provide a LOW level at the
output, the worst case supply voltages(s) shall be applied and the resultant current flow in the supply terminals measured.
3.3 I
CC
or I
EE
of combinatorial digital circuits. The inputs of the device under test shall be conditioned to put the device into
its worst case power dissipating state. The current flowing into the V
CC
, (positive supply) terminal, or out of the V
EE
(negative supply) terminal shall be measured with the V
CC
and V
EE
voltages at their maximum specified operating levels.
3.4 I
CC
or I
EE
of sequential digital circuits. The inputs of the device under test shall be exercised to put the device in a
known output state (either HIGH or LOW) that causes worst case power dissipation. The current flowing into the V
CC
(positive supply) terminal, or out of the V
EE
(negative supply) terminal shall be measured with the V
CC
and V
EE
voltages at
their maximum specified operating levels.
3.5 I
DD
(MOS logic gate). Inputs of the device under test shall be conditioned in such a way as to provide a HIGH level at
the output of MOS (P-Channel and C-MOS) or a LOW level at the output of MOS (N-Channel and C-MOS); worst case
voltage(s) shall be applied and the resultant current in the supply terminals measured.
3.6 I
GG
(MOS P-Channel and N-Channel logic gates). Inputs of the device under test shall be conditioned in such a way
as to provide a HIGH level at the output of MOS (P-Channel) or a LOW level at the output of MOS (N-Channel); worst case
voltage(s) shall be applied and the resultant current flow in the supply terminals measured.
3.7 I
DD
of MOS combinatorial circuits. See 3.3 above.
3.8 I
DD
of MOS sequential circuits. See 3.4 above.
3.9 I
GG
of MOS combinatorial circuits. See 3.3 above.
3.10 I
GG
of MOS sequential circuits. See 3.4 above.
3.11 I
DD
dynamic (MOS logic gating and flip flop circuits). The driving signal to the test circuit shall be provided according
to method 3001 of this standard; the worst case voltage(s) shall be applied and the resultant average current in the supply
terminals measured.