MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第504页

MIL-STD-883F METHOD 3012.1 15 November 1974 2 This page i ntenti onally lef t blank

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MIL-STD-883F
METHOD 3012.1
15 November 1974
1
METHOD 3012.1
TERMINAL CAPACITANCE
1. PURPOSE
. This method establishes the means for assuring circuit performance to the limits specified in the
applicable acquisition document in regard to terminal capacitance. This method applies to digital microelectronic devices,
such as TTL, DTL, RTL, ECL, and MOS.
2. APPARATUS
. The instrument shall be capable of applying a 1 MHz controllable amplitude signal superimposed on a
variable plus or minus dc voltage. The instrument will also have the capability of measuring the capacitance of this terminal
to within the limits and tolerance specified in the applicable acquisition document.
3. PROCEDURE
. This test may be performed at 25°C ±3°C. The capacitance measuring bridge shall be connected
between the input or output terminal and the ground terminal of the test circuit. The bridge shall be adjusted for a signal of 1
MHz, riding a bias level specified in the applicable acquisition document; the signal amplitude shall not exceed 50 mV rms.
With no device in the test socket the bridge shall then be zeroed. For capacitance values below 20 pF, the device shall be
connected directly to the bridge with leads as short as possible to avoid the effects of lead inductance. After inserting the
device under test and applying the specified bias conditions, the terminal capacitance shall be measured and compared to
the limits listed in the applicable acquisition document.
4. SUMMARY
. The following details shall be specified in the applicable acquisition document:
a. Circuit bias conditions.
b. Bias level at which measurements are to be made.
c. Maximum capacitance limits.
MIL-STD-883F
METHOD 3012.1
15 November 1974
2
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MIL-STD-883F
METHOD 3013.1
15 November 1974
1
METHOD 3013.1
NOISE MARGIN MEASUREMENTS FOR DIGITAL MICROELECTRONIC DEVICES
1. PURPOSE
. This method establishes the means of measuring the dc (steady- state) and ac (transient) noise margin of
digital microelectronic devices or to determine compliance with specified noise margin requirements in the applicable
acquisition document. It is also intended to provide assurance of interchangeability of devices and to eliminate
misunderstanding between manufacturers and users on noise margin test procedures and results. The standardization of
particular combinations of test parameters (e.g., pulse width, pulse amplitude, etc.) does not preclude the characterization of
devices under test with other variations in these parameters. However, such variations shall, where applicable, be provided
as additional conditions of test and shall not serve as a substitute for the requirements established herein.
1.1 Definitions
. The following definitions shall apply for the purposes of this test method:
a. Noise margin. Noise margin is defined as the voltage amplitude of extraneous signal which can be algebraically
added to the noise-free worst case "input" level before the output voltage deviates from the allowable logic voltage
levels. The term "input" (in quotation marks) is used here to refer to logic input terminals or ground reference
terminals.
b. DC noise margin. DC noise margin is defined as the dc voltage amplitude which can be algebraically added to the
noise-free worst case "input" level before the output exceeds the allowable logic voltage levels.
c. AC noise margin. AC noise margin is defined as the transient or pulse voltage amplitude which can be
algebraically added to the noise-free worst case "input" level before the output voltage exceeds the allowable logic
voltage levels.
d. Maximum and minimum. Maximum and minimum refer to an algebraic system where "max" represents the most
positive value of the range and "min" represents the least positive value of the range.
1.2 Symbols
. The following symbols shall apply for the purposes of this test method and shall be used in accordance with
the definitions provided (see 1.2.1, 1.2.2, and 1.2.3) and depicted on figures 3013-1, 3013-2, and 3013-3.
1.2.1 Logic levels
.
V
IL
max: The maximum allowed input LOW level in a logic system.
V
IL
min: The minimum allowed input LOW level in a logic system.
V
IH
max: The maximum allowed input HIGH level in a logic system.
V
IH
min: The minimum allowed input HIGH level in a logic system.
V
OL
max: The maximum output LOW level specified for a digital microelectronic device.
V
OL
max is also the noise-free worst case input LOW level, V
OL
(max) < V
IL
(max)
V
OH
min: The minimum output HIGH level specified for a digital microelectronic device.
V
OH
min is also the noise-free worst case input HIGH level, V
OH
(min) > V
IH
(min)
1.2.2 Noise margin levels
.
V
NL
: The LOW level noise margin or input voltage amplitude which can be algebraically added to V
OL
(max) before
the output level exceeds the allowed logic level.
V
NH
: The HIGH level noise margin or input voltage amplitude which can be algebraically added to V
OH
(min) before
the output level exceeds the allowed logic level.
V
NG+
: The positive voltage which can be algebraically added to the ground level before the output exceeds the
allowed logic level determined by worst case logic input levels.
*