MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第522页

MIL-STD-883F METHOD 3016 29 November 1985 2 3.1 Activati on time, maximum s upply voltage, t AH . Avail able tes t equipment has inherent delays ( due to tes t progr am stat ement execution, voltage dr iver r ise/ fall t…

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MIL-STD-883F
METHOD 3016
29 November 1985
1
METHOD 3016
ACTIVATION TIME VERIFICATION
1. PURPOSE
. This method establishes a means for assuring circuit performance during cold temperature start up. It
defines an activation time for digital microelectronic devices such as TTL, DTL, RTL, ECL, and MOS and establishes the
procedure necessary to accomplish the required testing. This method will ensure that a specified capability is available a
known time interval after application of power.
1.1 Definitions
. The following definitions shall apply for the purposes of this test method:
a. Activation time. Activation time is defined as the time required for a device to become functionally operable after
initial power is applied at the operating temperature extremes as specified by the applicable acquisition document.
Note that activation time may be due to device and test system limitations, or both.
b. Maximum and minimum. Maximum and minimum refer to an algebraic system where "max" represents the most
positive value of the range and "min" represents the least positive value of the range. This is consistent with
MIL-STD-1331, 30.1 and 30.2 for logic levels only.
c. Maximum operating frequency. Maximum operating frequency is defined as the frequency of operation resulting
from use of the minimum clock period for devices requiring a clock, or the frequency of operation resulting from the
use of the minimum cycle time for devices not requiring a clock (such as memory devices) as specified in the
applicable acquisition document.
1.2 Symbols
. The following symbols and definitions shall apply for the purposes of this method.
1.2.1 Logic levels
.
a. V
LW
= worst case nominal low level logic input. The maximum allowable V
IL
specified in the applicable acquisition
document minus 100 millivolts to allow for uncertainty in the drive level capability of high speed functional test
equipment. (V
LW
= V
IL
(max) - 100 mV).
b. V
HW
= worst case nominal high level logic input. The minimum allowable V
IH
as specified by the applicable
acquisition document plus 100 millivolts (V
HW
= V
IH
(min) + 100 mV).
c. V
OH
(min) = minimum output high level specified for a digital microelectronic device.
d. V
OL
(max) = maximum output low level specified for a digital microelectronic device.
1.2.2 Activation times
.
a. t
AH
= maximum allowable activation time requirement, measured at V
CC
(max).
b. t
AL
= maximum allowable activation time requirement, measured at V
CC
(min).
2. APPARATUS
. An instrument shall be provided which has the capability of applying sequential logic patterns to the
device under test in accordance with the applicable acquisition document. The test instrument shall also be capable of
applying nominal power supply voltage(s) and monitoring the output for the specified logic levels. The output monitoring
circuit shall be of the double comparator type. The threshold voltage (trip point) for a comparator shall be V
OL
(max) and V
OH
(min) as specified in the applicable acquisition document. The test chamber shall be capable of maintaining the device
under test at any specified test temperature.
3. PROCEDURE.
The device shall be thermally stabilized at the minimum specified test temperature with no power
applied to the device. The specified power supply voltage and the specified input logic patterns using V
LW
and V
HW
input
voltage levels shall then be applied to the device under test and the outputs shall be monitored as described in section 2.
This functional test shall be performed at a speed of at least 75 percent of F(max) using a test vector pattern as called out in
the applicable acquisition document that has been designed for maximum fault coverage with no more than 4 K vectors.
MIL-STD-883F
METHOD 3016
29 November 1985
2
3.1 Activation time, maximum supply voltage, t
AH
. Available test equipment has inherent delays (due to test program
statement execution, voltage driver rise/fall times, etc.) between the time power is applied to the device under test and
actual execution of the test. Therefore, the activation time stated in the applicable acquisition document should not be
specified as less than the test system delay (even though device performance may be better). The test sequence shall be
as follows.
3.1.1 Device under test
. The device under test shall be thermally stabilized at the minimum specified test temperature,
with the device unpowered.
3.1.2 Device under test shall then be powered up at V
CC
(max). After waiting the time specified by T
AH
(taking into
account test equipment delays), the functional test pattern (using V
LW
and V
HW
) logic levels) shall be applied to verify proper
operation.
3.1.3 Repeat sequences 3.1.1 and 3.1.2 at the maximum specified test temperature
.
3.2 Activation time, minimum supply voltage, t
AL
. Repeat sequence described in 3.1.1 to 3.1.3 using a supply voltage of
V
CC
(min).
3.3 Failure criteria
. The device must pass the functional test pattern and is a failure if the device fails any single pattern or
vector in the specified test set.
4. SUMMARY
. The following details, when applicable, shall be as specified in the applicable acquisition document:
a. V
IL
(max).
b. V
IH
(min).
c. V
OH
(min).
d. V
OL
(max).
e. V
CC
(min).
f. V
CC
(max).
g. Test temperature (min and max operating temperature).
h. t
AH
(max).
i. t
AL
(max).
j. Functional test pattern (see 3).
k. Maximum operating frequency, F (max) (see 1.1.c).
MIL-STD-883F
METHOD 3017
29 May 1987
1
METHOD 3017
MICROELECTRONICS PACKAGE DIGITAL SIGNAL TRANSMISSION
1. PURPOSE
. This method establishes the means of evaluating the characteristic impedance, capacitance, and delay
time of signal lines in packages used for high frequency digital integrated circuits. It is intended to assure a match between
circuit performance and interconnecting wiring to minimize signal degradation.
1.1 Definitions
.
1.1.1 Characteristic impedance
. The impedance that a section of transmission line exhibits due to its ratio of resistance
and inductance to capacitance.
1.1.2 Delay time
. The time delay experienced when a pulse generated by a driver with a particular drive impedance is
propagated through a section of transmission line.
1.2 Symbols
.
R: Resistance
L: Inductance
C: Capacitance
t
pd
: Propagation delay time
2. APPARATUS
. The approaches for transmission performance measurements shall include a suitable time domain
reflectometer (TDR) (see 2.1) and dc resistance measuring equipment (see 2.2).
2.1 Time domain reflectometer
. The TDR used for this test shall have a system rise time for the displayed reflection that
is not less than 5 times and preferably 10 times the rise time (method 3004) for the candidate integrated circuits to be
packaged. Interconnecting cables and fixtures shall be designed such that this ratio is not degraded due to reflections and
ringing in the test setup.
2.2 DC resistance
. DC resistance measuring equipment and probe fixtures shall be capable of measuring the resistance
of the package leads and the chip-to- package interconnect media with an accurancy of no greater than ±10 percent of the
actual value including errors due to the mechanical probing interface contact resistance.
3. PROCEDURE
. The test equipment configuration shall be as shown on figure 3017-1 using a time domain
reflectometer as specified (see 2). The characteristic impedance (Z
o
), propagation time (t
pd
), resistance and load
capacitance (C
L
) shall be measured for all representative configurations as determined by a review of the package drawings,
and the intended applications (see 3.2 through 3.3).
3.1 General considerations
.
3.1.1 TDR measurements
. Accurate measurement of transmission performance of a package pin using a TDR requires
careful design and implementation of adapter fixtures to avoid reflections due to transmission line discontinuities in the
cables and junctions between the TDR and the package being tested. The accuracy of the measurement will be enhanced if
the coaxial cable used to interface to the package is of a characteristic impedance as close as possible to the package pin
impedance. The interface to the package should be a soldered connection and mechanical design of the actual
coax-to-package interface should minimize the length of the uncontrolled impedance section. Stripline interfaces are the
best method for surface mount package styles.
3.1.2 Test configurations
. Obtaining a good high frequency ground is also important. Connection of the package ground
plane (if the package design has one) to the test set-up ground plane should be accomplished with a pin configuration
similar to actual usage in the intended package applications.
Pin selection for testing may vary according to package complexity. For packages with very symmetrical pin configurations
only a few pins need be tested but configurations must include pins adjacent and nonadjacent to the ground pins. Packages
with complex wiring and interconnection media should be tested 100 percent.