MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第542页

MIL-STD-883F METHOD 3022 29 May 1987 2 This page i ntenti onally lef t blank

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MIL-STD-883F
METHOD 3022
29 May 1987
1
METHOD 3022
INPUT CLAMP VOLTAGE
1. PURPOSE
. This method establishes the means for assuring circuit performance to the limits specified in the
applicable acquisition document in regard to input voltage levels in a region of relatively low differential resistance that serve
to limit the input voltage swing. Input clamp voltage is specified as a maximum positive value (V
IC
POS) or the maximum
negative value (V
IC
NEG). This method applies to digital microelectronic devices.
2. APPARATUS
. The test chamber shall be capable of maintaining the device under test at any specified test
temperature. The test apparatus shall be capable of supplying the worst case power supply voltage and shall be capable of
loading the input of the circuit under test with the specified negative current or the specified positive current, both referred to
as I
IN
. Resistors may be used to simulate the applicable current levels.
3. PROCEDURE
. The device shall be stabilized at the specified test temperature. Apply worst-case power supply
voltage (V
CC
) to the V
CC
terminal. Force the specified negative current from or the positive current into the input under test
and measure the resultant input voltage. (NOTE: Any input for which the I
IL
would influence the negative input current (I
IN
)
should have V
IC
measured with the V
CC
terminal open). All input terminals not under test may be high, low, or open to
minimize or inhibit any outside factors (noise, transients, etc.) from affecting the test. Inputs shall be tested individually.
4. SUMMARY
. The following details shall be specified in the applicable acquisition document:
a. Test temperature.
b. Worst case power supply voltage.
c. Current to be forced from the input terminal.
d. V
IC
(POS) or V
IC
(NEG) maximum limit.
MIL-STD-883F
METHOD 3022
29 May 1987
2
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MIL-STD-883F
METHOD 3023.1
5 November 1999
1
METHOD 3023.1
STATIC LATCH-UP MEASUREMENTS
FOR DIGITAL CMOS MICROELECTRONIC DEVICES
Latchup shall be performed in accordance with EIA/JESD78 dated March 1997. EIA/JESD78 supersedes JEDEC-STD-17.