MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第544页

MIL-STD-883F METHOD 3023 5 November 1999 2 This page i ntenti onally lef t blank

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MIL-STD-883F
METHOD 3023.1
5 November 1999
1
METHOD 3023.1
STATIC LATCH-UP MEASUREMENTS
FOR DIGITAL CMOS MICROELECTRONIC DEVICES
Latchup shall be performed in accordance with EIA/JESD78 dated March 1997. EIA/JESD78 supersedes JEDEC-STD-17.
MIL-STD-883F
METHOD 3023
5 November 1999
2
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MIL-STD-883F
METHOD 3024
19 August 1994
1
METHOD 3024
SIMULTANEOUS SWITCHING NOISE MEASUREMENTS
FOR DIGITAL MICROELECTRONIC DEVICES
1. Purpose
. This method establishes the procedure for measuring the ground bounce (and V
CC
bounce) noise in digital
microelectronic devices or to determine compliance with specified ground bounce noise requirements in the applicable
acquisition document. It is also intended to provide assurance of interchangeability of devices and to eliminate
misunderstanding between manufacturers and users on ground bounce noise test procedures and requirements. This
procedure is not intended to predict the amount of noise generated on an end product board, but for use in measuring
ground bounce noise using a standardized method for comparing noise levels between logic families and vendors.
1.1 Definitions
. The following definitions shall apply for the purposes of this test method:
a. Ground bounce noise. The voltage amplitude (peak) of extraneous signals present on a low-level non-switching
output with a specified number of other outputs switching. Ground bounce noise on a logic low output can be of
sufficient amplitude to exceed the high level threshold of a receiver, or cause latch-up on unprotected CMOS
inputs.
b. V
CC
bounce noise. The voltage amplitude (peak) of extraneous signals present on a high-level non-switching
output with a specified number of other outputs switching. V
CC
bounce on a logic high output can be of sufficient
amplitude to exceed the low level threshold of a receiver, or cause latch-up on unprotected CMOS inputs.
c. Simultaneous switching noise. Noise generated across the inductance of a package pin as a result of the charge
and discharge of load capacitance through two or more transitioning output pins.
d. Quiet low. A non-switching output which is driving a nominal low level.
e. Quiet high. AQ non-switching output which is driving a nominal high level.
f. Signal skew. The amount of time measured between any two signal transitions at the 1.5 V voltage level (for TTL
threshold devices) and at V
CC
/2 (for CMOS threshold devices).
1.2 Symbols
. The following symbols shall apply for the purposes of this test method:
1.2.1 Logic levels
.
V
IL
max: The maximum allowed input low level on a digital microelectronic device.
V
IL
min: The minimum allowed input low level on a digital microelectronic device.
V
IH
max: The maximum allowed input high level on a digital microelectronic device.
V
IH
min: The minimum allowed input high level on a digital microelectronic device.