MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第596页

MIL-STD-883F METHOD 5004.11 18 June 2004 6 TABLE I. Clas s l evel S and level B s creeni ng - Conti nued. 12 / For c lass level B devi ces, the fi ne and gross seal t ests (3.1. 16) s hall be perf ormed s eparatel y or t…

100%1 / 708
MIL-STD-883F
METHOD 5004.11
18 June 2004
5
TABLE I. Class level S and level B screening
- Continued.
1
/ All lots shall be selected for testing in accordance with the requirements of method 5007 herein.
2
/ Unless otherwise specified, at the manufacturer's option, test samples for group B, bond strength (method 5005) may
be randomly selected prior to or following internal visual (method 5004), prior to sealing provided all other specification
requirements are satisfied (e.g., bond strength requirements shall apply to each inspection lot, bond failures shall be
counted even if the bond would have failed internal visual exam). Test method 2010 applies in full except when
method 5004, alternate 1 or alternate 2 (appendix A) is in effect (see 3.3).
3
/ For class level B devices, this test may be replaced with thermal shock method 1011, test condition A, minimum.
4
/ At the manufacturer's option, visual inspection for catastrophic failures may be conducted after each of the
thermal/mechanical screens, after the sequence or after seal test. Catastrophic failures are defined as missing leads,
broken packages, or lids off.
5
/ See appendix A of MIL-PRF-38535, A.4.6.3. The PIND test may be performed in any sequence after 3.1.4 and prior to
3.1.13.
6
/ Class level S devices shall be serialized prior to initial electrical parameter measurements.
7
/ Post burn-in electrical parameters shall be read and recorded (see 3.1.13, subgroup 1). Pre burn-in or interim
electrical parameters (see 3.1.9 and 3.1.11) shall be read and recorded only when delta measurements have been
specified as part of post burn-in electrical measurements.
8
/ When specified in the applicable device specification, 100 percent of the devices shall be tested for those parameters
requiring delta calculations.
9
/ Dynamic burn-in only. Test condition F of method 1015 and 3.4.2 herein shall not apply.
10
/ The reverse bias burn-in (see 3.1.12) is a requirement only when specified in the applicable device specification and is
recommended only for a certain MOS, linear or other microcircuits where surface sensitivity may be of concern. When
reverse bias burn-in is not required, interim electrical parameter measurements 3.1.11 are omitted. The order of
performing the burn-in (see 3.1.10) and the reverse bias burn-in may be inverted.
11
/ Functional tests shall be conducted at input test conditions as follows:
V
IH
= V
IH
(min) +20 percent, -0 percent; V
IL
= V
IL
(max) +0 percent, -50 percent; as specified in the most similar military
detail specification. Devices may be tested using any input voltage within this input voltage range but shall be
guaranteed to V
IH
(min) and V
IL
(max).
CAUTION: To avoid test correlation problems, the test system noise (e.g., testers, handlers, etc.) should be verified
to assure that V
IH
(min) and V
IL
(max) requirements are not violated at the device terminals.
*
MIL-STD-883F
METHOD 5004.11
18 June 2004
6
TABLE I. Class level S and level B screening
- Continued.
12
/ For class level B devices, the fine and gross seal tests (3.1.16) shall be performed separately or together, between
constant acceleration (3.1.5) and external visual (3.1.19). For class level S devices, the fine and gross seal tests
(3.1.16) shall be performed separately or together, between final electrical testing (3.1.15) and external visual (3.1.19).
In addition, for class level S and level B devices, all device lots (sublots) having any physical processing steps (e.g.,
lead shearing, lead forming, solder dipping to the glass seal, change of, or rework to, the lead finish, etc.) performed
following seal (3.1.16) or external visual (3.1.19) shall be retested for hermeticity and visual defects. This shall be
accomplished by performing, and passing, as a minimum, a sample seal test (method 1014) using an acceptance
criteria of a quantity (accept number) of 116(0), and an external visual inspection (method 2009) on the entire
inspection lot (sublot). For devices with leads that are not glass-sealed and that have a lead pitch less than or equal
to 1.27 mm (0.050 inch), the sample seal test shall be performed using an acceptance criteria of a quantity (accept
number) of 15(0). If the sample fails the acceptance criteria specified, all devices in the inspection lot represented by
the sample shall be subjected to the fine and gross seal tests and all devices that fail shall be removed from the lot for
final acceptance. For class level S devices, with the approval of the qualifying activity, an additional room temperature
electrical test may be performed subsequent to seal (3.1.16), but before external visual (3.1.19) if the devices are
installed in individual carriers during electrical test.
13
/ The radiographic (see 3.1.17) screen may be performed in any sequence after 3.1.8.
14
/ Only one view is required for flat packages and leadless chip carriers having lead (terminal) metal on four sides.
15
/ Samples shall be selected for testing in accordance with the specific device class and lot requirements of method
5005. See 3.5 of method 5005.
16
/ External visual shall be performed on the lot any time after 3.1.17 and prior to shipment, and all shippable samples
shall have external visual inspection at least subsequent to qualification or quality conformance inspection testing.
17
/ The manufacturer shall inspect the devices 100 percent or on a sample basis using a quantity/accept number of
116(0). If one or more rejects occur in this sample, the manufacturer may double the sample size with no additional
failures allowed or inspect the remaining devices 100 percent for the failed criteria and remove the failed devices from
the lot. If the double sample also has one or more failures, the manufacturer shall be required to 100 percent inspect
the remaining devices in the lot for the failed criteria. Reinspection magnification shall be no less than that used for
the original inspection for the failed criteria.
18
/ Radiation latch-up screen shall be conducted when specified in purchase order or contract. Latch-up screen is not
required for SOS, SOI, and DI technology when latch-up is physically not possible. At the manufacturer's option,
latch-up screen may be conducted at any screening operation step after seal.
3.3.2 Description of special electrical screening tests
. The special electrical screens shall consist of a series of electrical
tests each of which can be categorized as either a voltage stress test or a low level leakage test.
3.3.2.1 Voltage stress tests
. The purpose of voltage stress tests is to eliminate those failure mechanisms which are
voltage sensitive. These tests shall be designed such that each circuit element (including metallization runs) within the
microcircuit is stressed by an applied voltage which approaches or exceeds (under current limited conditions) the breakdown
voltage of the circuit element under test. For those elements which cannot be placed in a reverse bias mode, the applied
voltage must be equal to or greater than 120 percent of the normal operating voltage. Any device which exhibits abnormal
leakage currents at the specified applied voltage conditions shall be rejected. The number of stress tests being performed
will vary from a few for a simple gate to many for MSI or LSI functions.
MIL-STD-883F
METHOD 5004.11
18 June 2004
7
3.3.2.2 Low level leakage tests
. The purpose of the low level leakage tests (which must be performed after the voltage
stress tests) is to eliminate any device that exhibits abnormal leakage. Since leakage currents can be measured only at the
device terminals, the test conditions and limits will vary depending upon the type of device being tested and the function of
the terminal under test (V
CC
, input, output, etc.). However, there may be cases where this test cannot be performed, i.e.,
input terminals which are forwarded biased junctions or resistive networks. But, since these types of circuits are generally
very sensitive to leakage currents, the device would fail parametrically if abnormal leakage currents were present. For all
other cases, where these measurements can be made, the tests shall be designed as described below:
a. For inputs which can be reverse biased, measure the input leakage at each input terminal at a voltage level which
is equal to one-half the maximum rated input voltage for that device with the supply terminal grounded. The
maximum allowable input leakage shall be established as shown in 3.3.2.2.1. Inputs shall be tested individually
with all other input terminals grounded.
b. For outputs which can be reverse biased, measure the output leakage at each output terminal at a voltage which is
equal to the device's maximum rated input voltage with the supply terminal grounded (if possible). The maximum
allowable output leakage limit shall be established as shown in 3.3.2.2.1. The input terminals shall be all grounded
(if the supply terminal is grounded) or if the supply terminal is not grounded, the input terminals should be in such a
state that the output terminal under test is in the reverse biased mode. All outputs shall be tested.
c. Measure the supply terminal leakage current at a voltage which is equal to 80 percent of the voltage required to
forward-bias a single PN junction on the device under test. The maximum allowable supply terminal leakage shall
be established as shown in 3.3.2.2.1.
3.3.2.2.1 Establishing maximum leakage current limits
. The maximum allowable leakage current shall be the upper 3
sigma value as established through an empirical evaluation of three or more production lots which are representative of
current production. Any process change which results in a substantial shift in the leakage distribution shall be cause for
recalculation and resubmission of this limit. The low current sensitivity of the test system shall be no higher than 20 percent
of the expected mean value of the distribution.
3.4 Substitution of test methods and sequence
.
3.4.1 Stabilization bake
. Molybdenum-gold multilayered conductors shall be subject to stabilization bake in accordance
with method 1008, condition C immediately before performing internal visual inspection 3.1.3.
3.4.2 Accelerated testing
. When test condition F of method 1015 for temperature/time accelerated screening is used for
either burn-in (see 3.1.10) or reverse bias burn-in (see 3.1.12), it shall be used for both. Also, when devices have
aluminum/gold metallurgical systems (at either the die pad or package post), the constant acceleration test (3.1.5) shall be
performed after burn-in and before completion of the final electrical tests (3.1.15) (i.e., to allow completion of time limited
tests but that sufficient 100 percent electrical testing to verify continuity of all bonds is accomplished subsequent to constant
acceleration).