MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第597页

MIL-STD-883F METHOD 5004.11 18 June 2004 7 3.3.2. 2 Low level leak age tes ts . The purpos e of the l ow level leak age tes ts ( which mus t be perf ormed aft er the vol tage str ess t ests ) i s to el iminat e any devic…

MIL-STD-883F

METHOD 5004.11

18 June 2004

TABLE I. Class level S and level B screening

- Continued.

/ For class level B devices, the fine and gross seal tests (3.1.16) shall be performed separately or together, between

constant acceleration (3.1.5) and external visual (3.1.19). For class level S devices, the fine and gross seal tests

(3.1.16) shall be performed separately or together, between final electrical testing (3.1.15) and external visual (3.1.19).

In addition, for class level S and level B devices, all device lots (sublots) having any physical processing steps (e.g.,

lead shearing, lead forming, solder dipping to the glass seal, change of, or rework to, the lead finish, etc.) performed

following seal (3.1.16) or external visual (3.1.19) shall be retested for hermeticity and visual defects. This shall be

accomplished by performing, and passing, as a minimum, a sample seal test (method 1014) using an acceptance

criteria of a quantity (accept number) of 116(0), and an external visual inspection (method 2009) on the entire

inspection lot (sublot). For devices with leads that are not glass-sealed and that have a lead pitch less than or equal

to 1.27 mm (0.050 inch), the sample seal test shall be performed using an acceptance criteria of a quantity (accept

number) of 15(0). If the sample fails the acceptance criteria specified, all devices in the inspection lot represented by

the sample shall be subjected to the fine and gross seal tests and all devices that fail shall be removed from the lot for

final acceptance. For class level S devices, with the approval of the qualifying activity, an additional room temperature

electrical test may be performed subsequent to seal (3.1.16), but before external visual (3.1.19) if the devices are

installed in individual carriers during electrical test.

/ The radiographic (see 3.1.17) screen may be performed in any sequence after 3.1.8.

/ Only one view is required for flat packages and leadless chip carriers having lead (terminal) metal on four sides.

/ Samples shall be selected for testing in accordance with the specific device class and lot requirements of method

5005. See 3.5 of method 5005.

/ External visual shall be performed on the lot any time after 3.1.17 and prior to shipment, and all shippable samples

shall have external visual inspection at least subsequent to qualification or quality conformance inspection testing.

/ The manufacturer shall inspect the devices 100 percent or on a sample basis using a quantity/accept number of

116(0). If one or more rejects occur in this sample, the manufacturer may double the sample size with no additional

failures allowed or inspect the remaining devices 100 percent for the failed criteria and remove the failed devices from

the lot. If the double sample also has one or more failures, the manufacturer shall be required to 100 percent inspect

the remaining devices in the lot for the failed criteria. Reinspection magnification shall be no less than that used for

the original inspection for the failed criteria.

/ Radiation latch-up screen shall be conducted when specified in purchase order or contract. Latch-up screen is not

required for SOS, SOI, and DI technology when latch-up is physically not possible. At the manufacturer's option,

latch-up screen may be conducted at any screening operation step after seal.

3.3.2 Description of special electrical screening tests

. The special electrical screens shall consist of a series of electrical

tests each of which can be categorized as either a voltage stress test or a low level leakage test.

3.3.2.1 Voltage stress tests

. The purpose of voltage stress tests is to eliminate those failure mechanisms which are

voltage sensitive. These tests shall be designed such that each circuit element (including metallization runs) within the

microcircuit is stressed by an applied voltage which approaches or exceeds (under current limited conditions) the breakdown

voltage of the circuit element under test. For those elements which cannot be placed in a reverse bias mode, the applied

voltage must be equal to or greater than 120 percent of the normal operating voltage. Any device which exhibits abnormal

leakage currents at the specified applied voltage conditions shall be rejected. The number of stress tests being performed

will vary from a few for a simple gate to many for MSI or LSI functions.

MIL-STD-883F

METHOD 5004.11

18 June 2004

3.3.2.2 Low level leakage tests

. The purpose of the low level leakage tests (which must be performed after the voltage

stress tests) is to eliminate any device that exhibits abnormal leakage. Since leakage currents can be measured only at the

device terminals, the test conditions and limits will vary depending upon the type of device being tested and the function of

the terminal under test (V

, input, output, etc.). However, there may be cases where this test cannot be performed, i.e.,

input terminals which are forwarded biased junctions or resistive networks. But, since these types of circuits are generally

very sensitive to leakage currents, the device would fail parametrically if abnormal leakage currents were present. For all

other cases, where these measurements can be made, the tests shall be designed as described below:

a. For inputs which can be reverse biased, measure the input leakage at each input terminal at a voltage level which

is equal to one-half the maximum rated input voltage for that device with the supply terminal grounded. The

maximum allowable input leakage shall be established as shown in 3.3.2.2.1. Inputs shall be tested individually

with all other input terminals grounded.

b. For outputs which can be reverse biased, measure the output leakage at each output terminal at a voltage which is

equal to the device's maximum rated input voltage with the supply terminal grounded (if possible). The maximum

allowable output leakage limit shall be established as shown in 3.3.2.2.1. The input terminals shall be all grounded

(if the supply terminal is grounded) or if the supply terminal is not grounded, the input terminals should be in such a

state that the output terminal under test is in the reverse biased mode. All outputs shall be tested.

c. Measure the supply terminal leakage current at a voltage which is equal to 80 percent of the voltage required to

forward-bias a single PN junction on the device under test. The maximum allowable supply terminal leakage shall

be established as shown in 3.3.2.2.1.

3.3.2.2.1 Establishing maximum leakage current limits

. The maximum allowable leakage current shall be the upper 3

sigma value as established through an empirical evaluation of three or more production lots which are representative of

current production. Any process change which results in a substantial shift in the leakage distribution shall be cause for

recalculation and resubmission of this limit. The low current sensitivity of the test system shall be no higher than 20 percent

of the expected mean value of the distribution.

3.4 Substitution of test methods and sequence

3.4.1 Stabilization bake

. Molybdenum-gold multilayered conductors shall be subject to stabilization bake in accordance

with method 1008, condition C immediately before performing internal visual inspection 3.1.3.

3.4.2 Accelerated testing

. When test condition F of method 1015 for temperature/time accelerated screening is used for

either burn-in (see 3.1.10) or reverse bias burn-in (see 3.1.12), it shall be used for both. Also, when devices have

aluminum/gold metallurgical systems (at either the die pad or package post), the constant acceleration test (3.1.5) shall be

performed after burn-in and before completion of the final electrical tests (3.1.15) (i.e., to allow completion of time limited

tests but that sufficient 100 percent electrical testing to verify continuity of all bonds is accomplished subsequent to constant

acceleration).

MIL-STD-883F

METHOD 5004.11

18 June 2004

3.5 Electrical measurements.

3.5.1 Interim (pre and post burn-in) electrical parameters

. Interim (pre and post burn-in) electrical testing shall be

performed when specified, to remove defective devices prior to further testing or to provide a basis for application of percent

defective allowable (PDA) criteria when a PDA is specified. The PDA shall be 5 percent or one device, whichever is greater.

This PDA shall be based, as a minimum, on failures from group A, subgroup 1 plus deltas (in all cases where delta

parameters are specified) with the parameters, deltas and any additional subgroups (or subgroups tested in lieu of A-1)

subject to the PDA as specified in the applicable device specification or drawing. If no device specification or drawing

exists, subgroups tested shall at least meet those of the most similar device specification or Standard Microcircuit Drawing.

In addition, for class level S the PDA shall be 3 percent (or one device, whichever is greater) based on failures from

functional parameters measured at room temperature. For class level S screening where an additional reverse bias burn-in

is required, the PDA shall be based on the results of both burn-in tests combined. The verified failures after burn-in divided

by the total number of devices submitted in the lot or sublot for burn-in shall be used to determine the percent defective for

that lot, or sublot and the lot or sublot shall be accepted or rejected based on the PDA for the applicable device class. Lots

and sublots may be resubmitted for burn-in one time only and may be resubmitted only when the percent defective does not

exceed twice the specified PDA, or 20 percent whichever is greater. This test need not include all specified device

parameters, but shall include those measurements that are most sensitive to and effective in removing electrically defective

devices.

3.5.2 Final electrical measurements

. Final electrical testing of microcircuits shall assure that the microcircuits tested

meet the electrical requirements of the applicable device specification or drawing and shall include, as a minimum, all

parameters, limits, and conditions of test which are specifically identified in the device specification or drawing as final

electrical test requirements. Final electrical test requirements that are duplicated in interim (post burn-in) electrical test (see

3.1.15) need not be repeated as final electrical tests.

3.5.3 Radiation latch-up screen

. Latch-up screen shall be conducted when specified in purchase order or contract. Test

conditions, temperature, and the electrical parameters to be measured pre, post, and during the test shall be in accordance

with the specified device specification. The PDA for each inspection lot or class level S sublot submitted for radiation

latch-up test shall be 5 percent or one device, whichever is greater.

3.6 Test results

. When required by the applicable device specification or drawing, test results shall be recorded and

maintained in accordance with the general requirements of 4.2 of this standard and A.4.7 of appendix A of MIL-PRF-38535.

3.7 Failure analysis

. When required by the applicable device specification, failure analysis of devices rejected during any

test in the screening sequence shall be accomplished in accordance with method 5003, test condition A of this standard.

3.8 Defective devices

. All devices that fail any test criteria in the screening sequence shall be removed from the lot at the

time of observation or immediately at the conclusion of the test in which the failures was observed. Once rejected and

verified as a device failure, no device may be retested for acceptance.