MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第600页

MIL-STD-883F METHOD 5004.11 18 June 2004 10 APPENDIX A PURPOSE : This doc ument addres ses two probl ems. Fi rst , Test Method 2010 vis ual cr iteri a for waf er fab i nduced defec ts i s unsuit able for complex wafer pr…

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MIL-STD-883F
METHOD 5004.11
18 June 2004
9
4. SUMMARY
. The following details shall be specified:
a. Procedure paragraph if other than 3.1, and device class.
b. Sequence of test, test method, test condition, limit, cycles, temperature, axis, etc., when not specified, or if other
than specified (see 3).
c. Interim (pre and post burn-in) electrical parameters (see 3.5.1).
d. Burn-in test condition (see 3.1.10) and burn-in test circuit.
e. Delta parameter measurements or provisions for PDA including procedures for traceability where applicable (see
3.5.1).
f. Final electrical measurements (see 3.5.2).
g. Constant acceleration level (see 3.2).
h. Requirements for data recording and reporting, where applicable (see 3.6).
i. Requirement for failure analysis (see 3.7).
MIL-STD-883F
METHOD 5004.11
18 June 2004
10
APPENDIX A
PURPOSE
:
This document addresses two problems. First, Test Method 2010 visual criteria for wafer fab induced defects is
unsuitable for complex wafer process technologies, as in most cases the defects themselves cannot be seen through 200X
magnification. Secondly, no current alternate suitably addresses defect control of complex wafer fab technologies. Section
2 of this document describes the conditions under which this procedure is invoked. This document implements a new
technique for controlling and eliminating wafer fab induced defects, while preserving and extending the intent of the original
Test Method 2010 visual criteria.
The essence of this procedure revolves around the concept that it is a manufacturer's responsibility to define and
document its approach to defect reduction and control in a manner that is acceptable to the manufacturer and their
qualifying activity, as specified in section 3 of this document. This includes an understanding of the reliability impact of
wafer fab process-induced defects. It is expected that considerable dialogue will occur between a manufacturer and the
qualifying activity, resulting in mutually agreeable defect control procedures. This document is deliberately non-specific
regarding metrics such as defect sizes, defect densities, correlation and risks to allow adaptability for different process
technologies, different manufacturing control methods and continuous improvement. The procedures are specified in this
document with the intent that metrics and their values will be made more specific via dialogue between a manufacturer and
its qualifying activity.
Defect characterization is addressed in section 4 of this document. A key element in this section is understanding the
effects of process defects on final product reliability. This understanding can be achieved in many ways, including:
experimentation, review of pertinent literature and certain semiconductor traditions. The depth and scope of any
characterization will be determined by a manufacturer and its qualifying activity.
The concept of demonstration is discussed in many sections of this document. The methods for demonstrating defect
understanding have been made as diverse as possible to allow flexibility.
As described in section 9 of this document, results of defect characterization must be documented as well as the methods
for monitoring and controlling defect levels. The effectiveness of any screens that are used (in-line or end-of-line) must also
be documented. The ultimate requirements for demonstration and documentation will be determined between a
manufacturer and its qualifying activity. The qualifying activity will be concerned with maintenance of institutional knowledge
and the level to which a manufacturer understands: defect generation, control, reduction, prevention and the effects of
defects on product reliability.
This document makes the underlying assumption that a manufacturer will undertake efforts to continuously improve defect
levels (i.e. reduce these levels) in its wafer fabrication processes. As part of this assumption, it is expected that the
inspections, as outlined in section 5 of this document, will be used to acquire information for defect level reduction. The
intent is not to create inspections which "inspect in" quality, though screens of this nature may be a part of a manufacturer's
integrated defect control system. Rather, it is intended to provide an effective means of defect prevention, control and
reducing defects generated by the wafer process. Ideally, the manufacturer is striving to continually improve its control
systems.
Sections 6, 7 and 8 of this document deal with excursion containment, yield analysis and a system for unexpected failure.
This document makes extensive use of examples and attachments to illustrate key points and ways in which these points
could be implemented. The examples are intended to be no more than examples, illustrating how the items in this procedure
might be performed in a given instance. They are not intended to specify the way items must be done. A glossary of terms
is provided in section 100. of this document.
MIL-STD-883F
METHOD 5004.11
18 June 2004
11
APPENDIX A
Introduction
:
The evolution and progress in semiconductor fabrication technology require that new quality assurance methodologies be
employed which are applicable to small geometry and multiple metallization microcircuits. Removal of ineffective visual
inspections require an effective foreign material and defect control program early in the manufacturing process. It is the
intent of this procedure to define the key elements of such a program. It is the responsibility of each manufacturer to define
and document his approach to manufacturing defect reduction and control. This program shall be approved by the qualifying
activity.
The goal of this procedure is to assure that defects induced during the wafer fabrication process shall be minimized to
such an extent as to avoid non-conformance of product to device specifications or premature termination of its useful life. It
is expected that killer defects (as defined by the manufacturer) will not be found in the delivered product. It is expected that
critical defects (as defined by the manufacturer) will be controlled to meet the intended product life.
10. Scope
:
10.1 This procedure may be conducted for complex technology microcircuits when any of the following conditions exist:
a. Minimum horizontal geometries are equal to or less than 1.5 µm final dimension of any current carrying conductors
on the wafer, or
b. Interconnects (eg. metal, polysilicon) conducting current consist of three or more levels and the number of logical
gates exceeds 4000.
c. Opaque materials mask design features and either or both conditions A or B apply.
10.2 This procedure may be subject to review by the acquiring activity.
10.3 Any manufacturer required to be compliant with this procedure for complex microcircuits may extend it to other
devices (optional devices) that do not meet the conditions as specified in 10.1, conditions a through c herein. Extension
applies only if those optional devices are manufactured primarily on the same wafer process line to most of the same
process baseline (the majority of the fab equipment and process baseline used to fabricate required product as defined in
10.1, conditions a through c, is also used on extension product). All elements of the processes that are different for the
extension products must meet the requirements herein.
10.4 This procedure allows for the removal, modification or reduction of inspections and screens, as a result of process
improvements. For such changes, the process (and/or sub-process) must be sufficiently characterized to permit such
action. Data supporting these changes must be made available to the qualifying activity upon request.
10.5 This procedure is applicable only to wafer fabrication related defects. When using this procedure the manufacturer
is exempt from sections 3.1.1 (except as noted below), 3.1.2, 3.1.4, 3.1.5, 3.1.6 and 3.1.7 of conditions A and B of test
method 2010. Assembly induced defects (ie: scribe damage, probe damage, bond integrity, die surface scratches and
foreign material) shall be inspected at low power (30X to 60X) only, in accordance with sections 3.1.1.1, 3.1.1.6, 3.1.3 and
3.2.5 of test method 2010, conditions A and B as applicable.
10.6 This procedure does not override the requirements of any other government specifications, unless otherwise
specified herein.