MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第602页
MIL-STD-883F METHOD 5004.11 18 June 2004 12 APPENDIX A 20. APPLICABLE DOCUMENTS ( This s ecti on is not appl icabl e to this document. ) 30. Quali fying ac tivit y approval : 30.1 The manufac turer 's i mplementat i…
MIL-STD-883F
METHOD 5004.11
18 June 2004
11
APPENDIX A
Introduction
:
The evolution and progress in semiconductor fabrication technology require that new quality assurance methodologies be
employed which are applicable to small geometry and multiple metallization microcircuits. Removal of ineffective visual
inspections require an effective foreign material and defect control program early in the manufacturing process. It is the
intent of this procedure to define the key elements of such a program. It is the responsibility of each manufacturer to define
and document his approach to manufacturing defect reduction and control. This program shall be approved by the qualifying
activity.
The goal of this procedure is to assure that defects induced during the wafer fabrication process shall be minimized to
such an extent as to avoid non-conformance of product to device specifications or premature termination of its useful life. It
is expected that killer defects (as defined by the manufacturer) will not be found in the delivered product. It is expected that
critical defects (as defined by the manufacturer) will be controlled to meet the intended product life.
10. Scope
:
10.1 This procedure may be conducted for complex technology microcircuits when any of the following conditions exist:
a. Minimum horizontal geometries are equal to or less than 1.5 µm final dimension of any current carrying conductors
on the wafer, or
b. Interconnects (eg. metal, polysilicon) conducting current consist of three or more levels and the number of logical
gates exceeds 4000.
c. Opaque materials mask design features and either or both conditions A or B apply.
10.2 This procedure may be subject to review by the acquiring activity.
10.3 Any manufacturer required to be compliant with this procedure for complex microcircuits may extend it to other
devices (optional devices) that do not meet the conditions as specified in 10.1, conditions a through c herein. Extension
applies only if those optional devices are manufactured primarily on the same wafer process line to most of the same
process baseline (the majority of the fab equipment and process baseline used to fabricate required product as defined in
10.1, conditions a through c, is also used on extension product). All elements of the processes that are different for the
extension products must meet the requirements herein.
10.4 This procedure allows for the removal, modification or reduction of inspections and screens, as a result of process
improvements. For such changes, the process (and/or sub-process) must be sufficiently characterized to permit such
action. Data supporting these changes must be made available to the qualifying activity upon request.
10.5 This procedure is applicable only to wafer fabrication related defects. When using this procedure the manufacturer
is exempt from sections 3.1.1 (except as noted below), 3.1.2, 3.1.4, 3.1.5, 3.1.6 and 3.1.7 of conditions A and B of test
method 2010. Assembly induced defects (ie: scribe damage, probe damage, bond integrity, die surface scratches and
foreign material) shall be inspected at low power (30X to 60X) only, in accordance with sections 3.1.1.1, 3.1.1.6, 3.1.3 and
3.2.5 of test method 2010, conditions A and B as applicable.
10.6 This procedure does not override the requirements of any other government specifications, unless otherwise
specified herein.
MIL-STD-883F
METHOD 5004.11
18 June 2004
12
APPENDIX A
20. APPLICABLE DOCUMENTS (This section is not applicable to this document.)
30. Qualifying activity approval
:
30.1 The manufacturer's implementation of this procedure shall be validated (audited) by the qualifying activity. The
qualifying activity will issue a letter of suitability to the supplier, prior to delivery of compliant product. The letter of suitability
shall specify exactly what is covered (eg: description of wafer fab line, including: location, process baseline, optional devices
and technologies, etc.)
30.2 The qualifying activity shall recognize the need for auditor expertise in semiconductor wafer fabrication in order to
validate a line to the requirements herein. Expertise in semiconductor wafer fabrication consists of: an understanding of
wafer fabrication process flow, wafer fabrication process and measurement tools, wafer fabrication process chemistry and
physics, reliability physics and defect generation and control.
40. Characterization of defects and screening effectiveness
:
40.1 Products built using this procedure must have the process characterized to determine "non-critical" defects, "critical"
defects and "killer" defects and to understand their impact on reliability. The characterization must consider interactive
effects to the extent they have a reasonable probability of occurrence (eg: contact resistance change as affected by contact
critical dimension variations interacting with dielectric film thickness variations). Defect characterization must identify
categories of known defects (see 40.3), the source of each defect type (to the extent necessary to insure adequate defect
control) and their population (ie: random, variation from die to die within a wafer, variation from wafer to wafer within a lot,
variation from lot to lot, variation with date of manufacturer).
40.2 Methods and techniques for evaluating defect impact on reliability may include but are not limited to: designed
experimentation, failure modes and effects analysis (FMEA), characterization data, analysis of field failures, analysis of
unexpected failures at a manufacturer, historically available data such as public literature and proprietary information,
existing reliability data, device/ process modeling, etc. It is not necessary to understand the reliability impact of each and
every defect or defect combination(s); rather, the repeatable reliability performance of the delivered product must be
understood in the context of defects likely to be present in the wafer process line at the time of fabrication.
40.3 Categories of defects must include the following, as a minimum (unless these defects do not occur because of
process capability or other fundamental reasons):
DEFECTS
: EXAMPLES/TYPES/CONSIDERATIONS:
- Particles: Size and composition of particles for affected mask levels and source(s) of
variation.
- Conductive
Traces: Size, incidence and impact of imperfections (ie: scratches, voids, cracks,
etc.). Shorting potential (ie: extrusions, hillocks, stringers, bridging, etc.).
Most vulnerable areas where current carrying density violations may occur.
- Metal
Corrosion: Corrosion or corrosive elements present in metallization.
- Film
Delam: Delamination, poor adherence, excessive stress or coefficient of thermal
expansion mismatches.
- Misalign: Contact, via, poly/diff. alignment. Acceptable versus unacceptable
alignment matching.
MIL-STD-883F
METHOD 5004.11
18 June 2004
13
APPENDIX A
- Diffusion
Pattern
Violation: Bridging between wells, width reduction (resistors) and enlargement.
- Dielectric
Film
Faults: Blown contacts/via's, holes, cracking, active junction line exposure,
excessive thickness variations.
- Die Surface
Protection
Faults: Cracks, pinholes, scratches, voids, cornerholes, peeling/lifting, blistering,
bond pad clearance.
- Diffusion,
isolation
defects,
trenches,
guard rings,
other
techniques: Voids, notches in pattern diffusion, overlaps of diffusion, contact windows
tub-to-tub connections (except by design), etc.
DEFECTS
: EXAMPLES/TYPES/CONSIDERATIONS:
- Film
Resistor
Flaws: Scratches, voids, potential bridging, non-adherence, corrosion, alignment,
overlap between resistors and conductive traces, step coverage thinning,
composition (color) changes.
- Laser Trimmed
Film Resistor
Flaws: Kerf width, detritus, current carrying violations (resistor width).
- Foreign
Material: Foreign to process step/ structure (chemical stains, photoresist, ink, stains,
liquid droplets).
Note: See appropriate category figures in TM 2010 Conditions A and B
40.3.1 The following metallization concerns need to be addressed by the manufacturer in the process control procedures
used to demonstrate metal integrity.
a. Silicon consumption
b. Junction spiking
c. Silicon precipitates (nodules)
d. Copper nucleation
e. Nonplanarity
f. Undercutting