MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第603页

MIL-STD-883F METHOD 5004.11 18 June 2004 13 APPENDIX A - Diffusio n Pattern Violat ion: Bridgi ng between wells , widt h reduct ion (r esis tors ) and enlar gement. - Dielec tri c Film Faults: Blown contact s/vi a's…

MIL-STD-883F

METHOD 5004.11

18 June 2004

APPENDIX A

20. APPLICABLE DOCUMENTS (This section is not applicable to this document.)

30. Qualifying activity approval

30.1 The manufacturer's implementation of this procedure shall be validated (audited) by the qualifying activity. The

qualifying activity will issue a letter of suitability to the supplier, prior to delivery of compliant product. The letter of suitability

shall specify exactly what is covered (eg: description of wafer fab line, including: location, process baseline, optional devices

and technologies, etc.)

30.2 The qualifying activity shall recognize the need for auditor expertise in semiconductor wafer fabrication in order to

validate a line to the requirements herein. Expertise in semiconductor wafer fabrication consists of: an understanding of

wafer fabrication process flow, wafer fabrication process and measurement tools, wafer fabrication process chemistry and

physics, reliability physics and defect generation and control.

40. Characterization of defects and screening effectiveness

40.1 Products built using this procedure must have the process characterized to determine "non-critical" defects, "critical"

defects and "killer" defects and to understand their impact on reliability. The characterization must consider interactive

effects to the extent they have a reasonable probability of occurrence (eg: contact resistance change as affected by contact

critical dimension variations interacting with dielectric film thickness variations). Defect characterization must identify

categories of known defects (see 40.3), the source of each defect type (to the extent necessary to insure adequate defect

control) and their population (ie: random, variation from die to die within a wafer, variation from wafer to wafer within a lot,

variation from lot to lot, variation with date of manufacturer).

40.2 Methods and techniques for evaluating defect impact on reliability may include but are not limited to: designed

experimentation, failure modes and effects analysis (FMEA), characterization data, analysis of field failures, analysis of

unexpected failures at a manufacturer, historically available data such as public literature and proprietary information,

existing reliability data, device/ process modeling, etc. It is not necessary to understand the reliability impact of each and

every defect or defect combination(s); rather, the repeatable reliability performance of the delivered product must be

understood in the context of defects likely to be present in the wafer process line at the time of fabrication.

40.3 Categories of defects must include the following, as a minimum (unless these defects do not occur because of

process capability or other fundamental reasons):

DEFECTS

: EXAMPLES/TYPES/CONSIDERATIONS:

- Particles: Size and composition of particles for affected mask levels and source(s) of

variation.

- Conductive

Traces: Size, incidence and impact of imperfections (ie: scratches, voids, cracks,

etc.). Shorting potential (ie: extrusions, hillocks, stringers, bridging, etc.).

Most vulnerable areas where current carrying density violations may occur.

- Metal

Corrosion: Corrosion or corrosive elements present in metallization.

- Film

Delam: Delamination, poor adherence, excessive stress or coefficient of thermal

expansion mismatches.

- Misalign: Contact, via, poly/diff. alignment. Acceptable versus unacceptable

alignment matching.

MIL-STD-883F

METHOD 5004.11

18 June 2004

APPENDIX A

- Diffusion

Pattern

Violation: Bridging between wells, width reduction (resistors) and enlargement.

- Dielectric

Film

Faults: Blown contacts/via's, holes, cracking, active junction line exposure,

excessive thickness variations.

- Die Surface

Protection

Faults: Cracks, pinholes, scratches, voids, cornerholes, peeling/lifting, blistering,

bond pad clearance.

- Diffusion,

isolation

defects,

trenches,

guard rings,

other

techniques: Voids, notches in pattern diffusion, overlaps of diffusion, contact windows

tub-to-tub connections (except by design), etc.

DEFECTS

: EXAMPLES/TYPES/CONSIDERATIONS:

- Film

Resistor

Flaws: Scratches, voids, potential bridging, non-adherence, corrosion, alignment,

overlap between resistors and conductive traces, step coverage thinning,

composition (color) changes.

- Laser Trimmed

Film Resistor

Flaws: Kerf width, detritus, current carrying violations (resistor width).

- Foreign

Material: Foreign to process step/ structure (chemical stains, photoresist, ink, stains,

liquid droplets).

Note: See appropriate category figures in TM 2010 Conditions A and B

40.3.1 The following metallization concerns need to be addressed by the manufacturer in the process control procedures

used to demonstrate metal integrity.

a. Silicon consumption

b. Junction spiking

c. Silicon precipitates (nodules)

d. Copper nucleation

e. Nonplanarity

f. Undercutting

MIL-STD-883F

METHOD 5004.11

18 June 2004

APPENDIX A

g. Notching

h. Tunneling

i. Cusping

40.4 Defect characterization must identify and quantify non-critical defects, critical defects, and killer defects at each

mask level and establish action limits at the appropriate inspection steps. If 100% in-line or end-of-line production screens

are used to remove a specific defect, action limits and inspections may not be required at the affected mask level.

Characterization must determine the major sources of variations and the impact of defect attributes (ie: size, mass,

composition and quantity). Characterization must comprehend the effects of defects on the mask level being characterized

and their impact on subsequent mask levels, up to and including the final product. Characterization must encompass defect

behavior at worse case allowable processing locations (eg: worse case physical location for critical defect generation), at

worse case boundary conditions (ie: thickness, temperature, gas flow, etc.) and to worse case design rules. See

Attachment #1: Example of Defect Characterization.

40.5 In accordance with the results of defect characterization, the action limits for defects must be less than the level at

which the defects are known to adversely affect the reliability and performance of the device (the use of process "safety

margins" must be invoked, eg: if an aluminum line with a 25% notch is known to shorten the life of the device, then margin

limits for the notching must be accounted for, that is, the allowable notch limit must be less than 25%). By definition, any

observation of a killer defect (one or more) exceeds its action limit.

40.6 The results of the defect characterization shall be used to establish inspection sampling requirements (ie: sample

sizes and sampling frequency) and analytical techniques for in-line and end-of-line process inspections (see section 50).

40.7 The manufacturer shall establish a process baseline and put the process under formal change control after defect

characterization has been completed and in-line and end-of-line inspection steps are implemented. Any changes that

adversely affect the defects require re-characterization of the defects (eg #1: changing fabrication gowns may affect

particulate generation and must be determined if they are equivalent or better than gowns used when the original defect

characterization was completed, if better no further action, if worse, re-characterization of the line. eg #2: a change in HCl

(hydrochloric acid) chemical supplier requires comparative analysis of new supplier to old supplier, relative to trace

impurities, followed by an engineering evaluation to validate the impact on product. Discovery of excessive, new impurities

that could not be proven benign would require re-characterization before the new supplier could be used).

40.8 Any manufacturers' imposed in-line or end-of-line screens must demonstrate their effectiveness in eliminating killer

and critical defects in excess of their allowable action limit(s).

40.9 Any new defects that surface as a result of excursion containment, yield analysis, customer returns, inspection

procedures, (etc.) must be characterized in accordance with specifications in section 40.

50. Inspection and test system

50.1 Control and reduction of defects will result from an inspection and test system, employing process and product

monitors and screens. The inspection and test system is incorporated throughout the wafer fab process flow (in-line and/or

end-of-line). It is expected that an inspection and test system will prevent killer defects from appearing in the delivered

product. See Attachment #2: Example of an Inspection and Test System.

50.2 Inspection and test procedures shall form an integrated approach that in total controls and reduces defects. The

procedure shall consider the following criteria where applicable: