MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第660页

MIL-STD-883F METHOD 5010.4 18 June 2004 10 3.4.9 El ectr ical meas urements . 3.4.9. 1 Interi m (pre- and pos t-bur n-in) elect rical parameter s . Interi m (pre- and post- burn-i n) elect ric al test ing shal l be perfo…

MIL-STD-883F

METHOD 5010.4

18 June 2004

(1) Reduction of test must be considered separately for each wafer fabrication line and each die family.

(2) The manufacturer shall demonstrate that the wafer fabrication line that produces product which will involve

reduction of temperature cycles is capable and in process control.

(3) The manufacturer shall perform a high magnification visual inspection on a small sample of devices (e.g.,

5(0)) to monitor the process. This inspection may be performed at wafer level.

c. Special electrical screening tests shall be applied to each microcircuit die at the wafer, individual die (chip) and

packaged, or both, microcircuit level in accordance with the requirements of MIL-STD-883, method 5004, 3.3.2.

The conditions and limits of the electrical tests (in table III format) shall be submitted to the preparing activity for

approval and subsequently maintained on file with the qualifying activity. These special screens are in addition to

the required electrical parametric tests which the device must pass and shall be designed to screen out devices

with defects that were not inspected to the full criteria of 3.4.3 (internal visual). Due to the nature of these tests,

they are not to be repeated as part of the qualification and quality conformance procedures.

Alternate 2: The requirements and conditions for use of this alternate are contained in appendix A of method

5004. This option applies to both class level B and class level S microcircuits.

3.4.3 Stabilization bake

. Stabilization bake is not required for class level S or class level B product unless specified in the

device specification or drawing.

3.4.4 Visual inspection for damage

. The manufacturer may inspect for damage after each screening step. Damaged

devices shall be removed from the lot.

3.4.5 Temperature cycling or thermal shock

. All devices shall be subjected to the requirements of temperature cycling or

thermal shock. The device specifications or drawing shall specify which screen shall be employed. Temperature cycling

shall be in accordance with MIL-STD-883, method 1010, condition C minimum. For class level B, this test may be replaced

with thermal shock in accordance with MIL-STD- 883, method 1011, condition A minimum.

3.4.6 Constant acceleration

. All devices shall be subjected to constant acceleration, in the Y

axis only, in accordance

with MIL-STD-883, method 2001, condition E (minimum). Microcircuits which are contained in packages which have an

inner seal or cavity perimeter of two inches or more in total length or have a package mass of five grams or more may be

treated in accordance with provisions below as an alternate to this procedure. Delete test condition E and replace with test

condition D. Unless otherwise specified, the stress level for large, monolithic microcircuit packages shall not be reduced

below condition D. If the stress level specified is below condition D, the manufacture shall have data to justify this reduction

and this data must be maintained and available for review by the preparing or acquiring activity. The minimum stress level

allowed is condition A.

3.4.7 Particle impact noise detection test (PIND)

. Testing to be performed in accordance with appendix A of

MIL-PRF-8535, A.4.6.3. The PIND test may be performed in any sequence after temperature cycling and prior to final

electrical test.

3.4.8 Seal (fine and gross leak) testing

. For class level S devices seal testing may be performed in any sequence

between the final electrical test and external visual, but it shall be performed after all shearing and forming operations on the

terminals. For class level B devices, fine and gross seal test shall be performed separate or together in any sequence and

order between 3.4.7 and 3.4.13 and they shall be performed after all shearing and forming operations on the terminals.

When the 100 percent seal screen cannot be performed following all shearing or forming operations (i.e., flat packs, brazed

lead packages, and chip carriers) the seal screen shall be done 100 percent prior to those shearing and forming operations

and a sample test using sample size number of 45 (C = 0) shall be performed on each inspection lot following these

operations to verify integrity. For devices with leads that are not glass-sealed and that have a lead pitch less than or equal

to 1.27 mm (0.050 inch), the sample seal test shall be performed using an acceptance criteria of a quantity (accept number)

of 15 (0). If sample fails the sample acceptance criteria, all devices in the inspection lot represented by the sample tested

shall be subjected to and pass 100 percent fine and gross leak seal screens.

MIL-STD-883F

METHOD 5010.4

18 June 2004

3.4.9 Electrical measurements.

3.4.9.1 Interim (pre- and post-burn-in) electrical parameters

. Interim (pre- and post-burn-in) electrical testing shall be

performed when specified, to remove defective devices prior to further testing or to provide a basis for application of percent

defective allowable (PDA) criteria when a PDA is specified. The PDA shall be 5 percent or one device, whichever is greater.

This PDA shall be based, as a minimum, on failures from group A, subgroup 1 plus deltas (in cases where delta parameters

are specified) with the parameters, deltas, and any additional subgroups (or subgroups tested in lieu of A-1) subject to the

PDA as specified in the applicable device specification or drawing. If no device specification or drawing exists, subgroups

tested shall at least meet those of the most similar device specification or Standard Microcircuit Drawing. In addition, for

class level S the PDA shall be 3 percent (or one device, whichever is greater) based on failures from functional parameters

measured at room temperature. For class level S screening, where an additional reverse bias burn-in is required, the PDA

shall be based on the results of both burn-in tests combined. The verified failures after burn-in divided by the total number

of devices submitted in the lot or sublot for burn-in shall be used to determine the percent defective for that lot, or sublot and

the lot or sublot shall be accepted or rejected based on the PDA for the applicable device class. Lots and sublots may be

resubmitted for burn-in one time only and may be resubmitted only when the percent defective does not exceed twice the

specified PDA, or 20 percent, whichever is greater.

3.4.9.2 Pattern failures

. Pattern failure criteria may be used as an option for class level B, provided that:

a. Inspection lot size is less than 500 devices.

b. Pre burn-in electrical testing is done.

3.4.9.2.1 Pattern failures criteria

. A maximum number of pattern failures (failures of the same part type when the failures

are caused by the same basic failure mechanism) shall apply as specified in the acquisition document. If not otherwise

specified, the maximum allowable pattern failures shall be five. Accountability shall include burn-in through final electrical

test.

3.4.9.2.2 Pattern failure resubmission

. When the number of pattern failures exceeds the specified limits, the inspection

lot shall be rejected. At the manufacturer's option, the rejected lot may be resubmitted to burn-in one time provided:

a. The cause of the failure has been evaluated and determined.

b. Appropriate and effective corrective action has been completed to reject all devices affected by the failure cause.

c. Appropriate preventive action has been initiated.

3.4.10 Burn-in

. Device burn-in shall be performed in accordance with the requirements of method 1015 conditions A, B,

C, D, or E. Regardless of power level, devices shall be able to be burned-in at their maximum rated operating temperature.

For devices whose maximum operating temperature is stated in terms of ambient temperature, T

, table I of method 1015

applies. For devices whose maximum operating temperature is stated in terms of case temperature, T

, and where the

ambient temperature would cause T

to exceed 200°C for class level B or 175°C for class level S, the ambient operating

temperature may be reduced during burn-in from 125°C to a value that will demonstrate a T

between 175°C and 200°C (for

both class levels S and B) and T

equal to or greater than 125°C without changing the test duration. Data supporting this

reduction shall be available to the acquiring and qualifying activities upon request.

3.4.11 Final electrical measurements

. Final electrical testing of microcircuits shall assure that the microcircuits tested

meet the electrical requirements of the applicable device specification or drawing and shall include, as a minimum, the tests

of group A, subgroups 1, 2, 3, 4 or 7, 5 and 6, or 8, and 9.

3.4.12 Radiographic

. The radiographic screen may be performed in any sequence after PIND test and before external

visual inspection. Only one view is required for flat packages and leadless chip carriers having lead (terminal) metal on four

sides.

3.4.13 External visual inspection

. All devices shall be inspected in accordance with MIL-STD-883, method 2009, prior to

acceptance for shipment

MIL-STD-883F

METHOD 5010.4

18 June 2004

3.5 Qualification and quality conformance procedures

. Qualification and quality conformance shall be performed in

accordance with A.4.4 qualification procedures and A.4.5 quality conformance inspection of appendix A of MIL-PRF-38535

except as modified herein. The qualification device shall be used for QCI testing in accordance with 3.5.3 herein, as well as

for qualifying the process line. Life testing requirements shall follow the same criteria as burn-in (3.4.10 herein) for reduced

temperature.

3.5.1 Qualification testing

. Initial product process qualification shall be in accordance with MIL-STD-883 method 5005.

Change to qualified product shall be addressed in accordance with MIL-STD-883, method 5005 and appendix A of

MIL-PRF-38535, A.3.4.2. The SEC shall be used for group D inspection whenever practical; where the SEC cannot be

used, another die may be used (for gate arrays, 60 percent or greater utilization required). Utilizing the qualification device

the process monitor, the manufacturer shall demonstrate:

a. Process control and stability.

b. Process/device reliability.

c. Design and simulation control.

3.5.1.1 Detailed qualification test plan

. The manufacturer shall submit to the qualifying activity for approval a detailed

qualification test plan to assure conformance to 3.5.1 herein. The test plan shall, as a minimum, define test groups,

subgroups, conditions, and sampling plans in accordance with method 5005, as well as the tests to carry out 3.5.1.2,

3.5.1.3, and 3.5.1.4.

3.5.1.2 Database test

. For qualification, at least five PM's per wafer (located in accordance with appendix II) shall be

measured to ensure the establishment of a statistically valid database on which a decision can be made as to whether the

manufacturer's process is stable and under control.

3.5.1.3 Qualification device design and test plan

. Qualification device design and test plan to be used to qualify the

manufacturing line shall be submitted to the qualifying activity for approval. The design must meet the minimum

requirements of 3.3.4.2 herein. The test plan must include life test requirements. If a SEC is used as the qualification

device, data demonstrating process reliability from lots processed within 12 months of qualification and that an on-going

SEC program is in effect shall be submitted for qualifying activity review.

3.5.1.4 Design and simulation verification

. Design and simulation verification shall be accomplished as follows:

a. Design rule check (DRC) verification. DRC software shall be run on a design which contains known design rule

violations.

b. Electrical rule check (ERC) verification. ERC software shall be run on a design which contains known electrical

rule violations (e.g., fan-out violations).

c. Layout versus schematic (LVS) check.

d. Correct by construction. If the manufacturers' design methodology is based on a "correct by construction"

approach, distinct DRC, ERC, and LVS software is unnecessary and a, b, and c above do not apply. However,

the manufacturer shall provide suitable data to demonstrate the correct performance of "correct by construction"

software.

e. Computer aided design (CAD) system control shall be in accordance with appendix I herein.

3.5.2 Quality conformance inspection

. This procedure, as applicable to the microcircuit type and class, shall apply for all

quality conformance inspection requirements. Subgroups within a group of tests may be performed in any sequence but

individual tests within a subgroup (except group B, subgroup 2) shall be performed in the sequence indicated for groups B,

C, D, and E tests herein. Where end-point electrical measurements are required for subgroups in groups B, C, D, and E

testing herein, they shall be as specified in the applicable device specification or drawing. Where end-point measurements

are required but no parameters have been identified in the acquisition document for this purpose, the final electrical

parameters specified for 100 percent screening shall be used as end-point measurements. Electrical reject devices from the

same inspection lot may be used for all subgroups when end-point measurements are not required.

3.5.2.1 Radiation hardness

. Quality conformance inspection requirements for radiation hardness assured devices are in

addition to the normal class level S and B requirements. Those requirements are detailed in table VIII (group E) herein. The

radiation levels (M, D, P, L, R, F, G and H) are defined in appendix A of MIL-PRF-38535.