MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第673页

MIL-STD-883F METHOD 5010.4 18 June 2004 23 APPENDIX I 30.5. Des ign rul e check ing . a. Are des ign cons trai nts enf orced by the c ustomer s or management, such as: Synchron ous des igns onl y? Use of an appr oved set…

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

30.2 Design process

a. Who does and who approves the various levels of design?

Requirements definition? Detail function definition? Detail design (e.g., gate level design)? Layout and mask

generation?

b. What automatic aids are used for refinement from each design level to the next?

c. What automatic aids are used for verifying the refinement at each level (e.g., automatic checking of layout versus

schematic)?

d. How is automatic placement and routing software verified and certified for use?

30.3 Simulation

a. What simulators are used for:

Process simulation (e.g., SUPREME-II)?

Circuit simulation (e.g., SPICE, SCEPTRE)?

Gate level simulation (e.g., LASAR HITS)?

Switch level simulation?

Behavior/function simulation?

Dynamic timing analysis (to include actual delays due to placement and routing?

b. How are the above simulators verified? Are benchmarks used, and if so, what are these benchmarks?

c. Are the simulation results periodically checked against actual silicon test data (to complete the loop)?

30.4. Test

a. What test tools are used for:

Automatic test vector generation?

Fault simulation?

Insertion of design-for-testability/built-in-test features? (And are they integrated with the design process?)

b. Who is responsible for test generation:

Foundry?

Customer?

Designer?

c. If test vectors are not generated by the foundry, are the submitted vectors evaluated by the foundry to determine

the percentage of faults detected?

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

30.5. Design rule checking

a. Are design constraints enforced by the customers or management, such as:

Synchronous designs only?

Use of an approved set of cells/macrocells only?

Conservative use of electrical and switching limits?

Is the designer able to obtain waivers?

b. What design rule checkers (DRCs) are used for:

Physical rule checks (e.g., minimum spacing)?

Electrical rule checks (e.g., max current density, fanout restrictions)? Timing rule checks (e.g., worst-case timing

paths)? Logical rule checks (e.g., unclocked feedback paths)?

c. Is each design subjected to the above DRCs?

d. How can the DRC software be shown to "work as advertised?"

e. If "correct by construction" techniques are used, what procedure is used, how is "correctness" assured?

30.6. Software control

a. What are the sources of design and test software?

Own organization?

Workstation vendors?

Outside commercial vendors?

Universities?

b. How is design and test software approved and controlled:

Frequency of major/minor revision?

Trouble reports?

Regression testing?

c. What commercial CAD/CAE work stations or packages are used (e.g., MENTOR, Daisy, Silvar-Lisco)? Are

modifications to any of the software packages permitted?

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

30.7. How is interface with foundries and customers, or both done

Data formats?

Media (e.g., magtapes, modems, DDN/Arpanet)?

Qualification of foundry via test chips?

Are evaluation chips available for customers to assess performance?

30.8. Who tests the chips

At wafer level?

After packaging?

Burn-in?

Life testing?

What automatic test equipment types are used?

30.9. Masks

a. What are the procedures for mask making, inspection, verification, and repair?

b. Is the design transferred to the fab house via an actual mask set or via software?

c. If design transfer is via software, what are the procedures used to verify the mask design?

30.10. Wafer acceptance

a. What wafer inspection/accept-reject criteria are currently used (i.e., how is process control/stability

demonstrated)?

b. Which of the following process control indicators are used?

Kerf test structure measurements? (What structures are in the kerf; how many kerf sites are measured; what data

are taken; tolerances allowed?)

Drop-ins: (What does the drop-in design consist of? How many drop-ins per wafer? Allowed parameter

tolerances?)

Visual test structures?

c. How is high magnification inspection being accomplished? Are voltage stress tests used in lieu of some of the

high mag inspections?