MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第674页

MIL-STD-883F METHOD 5010.4 18 June 2004 24 APPENDIX I 30.7. How i s inter face wit h foundries and cus tomers , or both done ? Data formats? Media (e.g. , magtapes , modems , DDN/Ar panet)? Qualif icat ion of f oundry vi…

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

30.5. Design rule checking

a. Are design constraints enforced by the customers or management, such as:

Synchronous designs only?

Use of an approved set of cells/macrocells only?

Conservative use of electrical and switching limits?

Is the designer able to obtain waivers?

b. What design rule checkers (DRCs) are used for:

Physical rule checks (e.g., minimum spacing)?

Electrical rule checks (e.g., max current density, fanout restrictions)? Timing rule checks (e.g., worst-case timing

paths)? Logical rule checks (e.g., unclocked feedback paths)?

c. Is each design subjected to the above DRCs?

d. How can the DRC software be shown to "work as advertised?"

e. If "correct by construction" techniques are used, what procedure is used, how is "correctness" assured?

30.6. Software control

a. What are the sources of design and test software?

Own organization?

Workstation vendors?

Outside commercial vendors?

Universities?

b. How is design and test software approved and controlled:

Frequency of major/minor revision?

Trouble reports?

Regression testing?

c. What commercial CAD/CAE work stations or packages are used (e.g., MENTOR, Daisy, Silvar-Lisco)? Are

modifications to any of the software packages permitted?

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

30.7. How is interface with foundries and customers, or both done

Data formats?

Media (e.g., magtapes, modems, DDN/Arpanet)?

Qualification of foundry via test chips?

Are evaluation chips available for customers to assess performance?

30.8. Who tests the chips

At wafer level?

After packaging?

Burn-in?

Life testing?

What automatic test equipment types are used?

30.9. Masks

a. What are the procedures for mask making, inspection, verification, and repair?

b. Is the design transferred to the fab house via an actual mask set or via software?

c. If design transfer is via software, what are the procedures used to verify the mask design?

30.10. Wafer acceptance

a. What wafer inspection/accept-reject criteria are currently used (i.e., how is process control/stability

demonstrated)?

b. Which of the following process control indicators are used?

Kerf test structure measurements? (What structures are in the kerf; how many kerf sites are measured; what data

are taken; tolerances allowed?)

Drop-ins: (What does the drop-in design consist of? How many drop-ins per wafer? Allowed parameter

tolerances?)

Visual test structures?

c. How is high magnification inspection being accomplished? Are voltage stress tests used in lieu of some of the

high mag inspections?

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

30.11. Reliability evaluation

a. How is the reliability of the process proven? It is done via:

Standard evaluation chips (SECs) or reliability evaluation chips?

Test dice with specialized/optimized test structures?

b. If such vehicles do not exist, how is the processing shown to be free of reliability hazards?

c. How can the power buses be guaranteed to be within current density specifications at all times and under all

conditions?

d. For CMOS technology, how is a latch-up free process assured?

e. For bipolar technology, is any radiation hardness characterization done?

30.12. Documentation

a. What are the procedures for certifying and controlling the configuration of software?

b. What are the procedures outlining in detail the process flows for computer-aided

design/manufacture/engineering/test (CAD/M/E/T)?

c. If neither of above is available, when will they be available?