MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第697页

MIL-STD-883F METHOD 5012.1 27 July 199 0 3 2. APPARATUS . 2.1 Logic simul ator . Implement ation of t his t est proc edure requi res the use of a facilit y capable of simul ating the beha vior of faul t-f ree digit al lo…

MIL-STD-883F

METHOD 5012.1

27 July 1990

e. Failure hierarchy: Failure mechanism, physical failure, logical fault, error. The failure hierarchy relates physical

defects and their causes to fault simulators and observable effects. A failure mechanism is the actual cause of

physical failure; an example is electromigration of aluminum in a microcircuit. A physical failure (or simply failure)

is the actual physical defect caused by a failure mechanism; an example is an open metal line. A logical fault (or

simply fault) is a logical abstraction of the immediate effect of a failure; an example is "stuck- at-one" behavior of a

logic gate input in the presence of an open metal line. An error is a difference between the behavior of a fault-free

and faulty DUT at one or more observable primary outputs of the DUT.

f. Fault coverage

. For a logic model of a DUT, a fault universe for the logic model of the DUT, and a given test

vector sequence, fault coverage is the fraction obtained by dividing the number of faults contained in the fault

universe that are detected by the test vector sequence by the total number of faults contained in the fault

universe. Fault coverage is also stated as a percentage. In this test procedure, fault coverage is understood to be

based on the detectable fault equivalence classes (see 3.3). Rounding of fault coverage fractions or percentages

shall be "toward zero," not "to nearest." For example, if 9,499 faults are detected out of 10,000 faults simulated,

the fault coverage is 94.99 percent; if this value is to be rounded to two significant digits, the result shall be

reported as 94 percent, not 95 percent.

g. Logic line, node

. Logic lines are the connections between components in a logic model, through which logic

signals flow. Logic lines are the idealized "wires" in a logic model. A set of connected logic lines is a node.

h. Logic: Combinational and sequential

. Combinational digital logic contains only components that do not possess

memory, and in which there are no feedback paths. Sequential digital logic contains at least one component that

contains memory, or at least one feedback path, or both. For example, a flip-flop is a component that contains

memory, and cross-coupled logic gates introduce feedback paths.

i. Macro

. A logic modeling convention representing a model contained within another model. A macro boundary

does not necessarily imply the existence of a physical boundary in the logic model. A main model is a logic model

that is not contained within a larger model. Macros may be nested (that is, a macro may contain submacros).

j. Primary inputs, primary outputs

. Primary inputs to a logic model represent the logic lines of a DUT that are driven

by the ATE's drivers and thus are directly controllable test points. Primary outputs from a logic model represent

the logic lines of the DUT that are sensed by the ATE's comparators and thus are directly observable test points.

The inputs to the "main model" of the logic model of the DUT are the primary inputs, and the outputs from the

main model are the primary outputs. Internal nodes that can be driven or sensed by means of special test modes

shall be considered to be control or observation test points.

k. Test effectiveness

. A measure similar to fault coverage, but used in lieu of fault coverage in cases where physical

failures cannot be modeled accurately as logical faults. For example, many RAM and PLA failures cannot be

idealized conveniently in the same way as gate-level failures. However, established test algorithms may be used

to detect essentially all likely physical failures in such structures.

l. Test vector sequence

. The (ordered) sequence of stimuli (applied to a logic model of a DUT) or

stimulus/response values (applied to, and compared for, the actual DUT by the ATE).

m. Undetectable and detectable faults

. An undetectable fault is defined herein as a logical fault for which no test

vector sequence exists that can cause at least one hard detection or potential detection (see 1.1c). Otherwise

(that is, some test vector sequence exists that causes at least one hard detection, or potential detection, or both),

the fault is defined herein to be a detectable fault (see 3.3.3).

MIL-STD-883F

METHOD 5012.1

27 July 1990

2. APPARATUS

2.1 Logic simulator

. Implementation of this test procedure requires the use of a facility capable of simulating the behavior

of fault-free digital logic in response to a test vector sequence; this capability is herein referred to as logic simulation.

In order to simulate sequential digital logic, the simulator must support simulation of a minimum of four logic states: zero (0),

one (1), high-impedance (Z), and unknown (X). In order to simulate combinational digital logic only, the simulator must

support simulation of a minimum of two logic states: 0 and 1.

At the start of logic simulation of a logic model of a DUT containing sequential logic, the state of every logic line and

component containing memory shall be X; any other initial condition, including explicit initialization of any line or memory

element to 0 or 1, shall be documented and justified in the fault simulation report.

In order to simulate wired connections or bus structures, the simulator must be capable of resolving signal conflicts

introduced by such structures. Otherwise, modeling workarounds shall be permitted to eliminate such structures from the

logic model (see 3.1.2).

In order to simulate sequential digital logic, the simulator must support event- directed simulation. As a minimum, unit-delay

logic components must be supported.

Simulation of combinational-only logic, or simulation of sequential logic in special cases (such as combinational logic

extracted from a scannable sequential logic model) can be based on nonevent-directed simulation, such as levelized,

zero-delay, or compiled-code methods. The fault simulation report shall describe why the selected method is equivalent to

the more general event-directed method.

2.2 Fault simulator

. In addition to the capability to simulate the fault-free digital logic, the capability is also required to

simulate the effect of single, permanent, stuck-at-zero and stuck-at-one faults on the behavior of the logic; this capability is

herein referred to as fault simulation. Fault simulation shall reflect the limitations of the target ATE (see 3.4.1). It is not

necessary that the fault simulator directly support the requirements of this test procedure in the areas of hard versus

potential detections, fault universe selection, and fault classing. However, the capability must exist, at least indirectly, to

report fault coverage in accordance with this procedure. Where approximations arise (for example, where fault classing

compensates for a different method of fault universe selection) such differences shall be documented in the fault simulation

report, and it shall be shown that the approximations do not increase the fault coverage obtained.

3. PROCEDURE

3.1 Logic model

3.1.1 Level of modeling

. The DUT shall be described in terms of a logic model composed of components and

connections between components. Primary inputs to the logic model are assumed to be outputs of an imaginary component

(representing the ATE's drivers), and primary outputs of the logic model are assumed to be inputs to an imaginary

component (representing the ATE's comparators). Some logic simulators require that the ATE drivers and comparators be

modeled explicitly; however, these components shall not be considered to be part of the logic model of the DUT.

3.1.2 Logic lines and nodes (see 1.1g)

. All fan-out from a node in a logic model is ideal, that is, fan-out branches

associated with a node emanate from a single point driven by a fan-out origin. All fan-in to a node in a logic model is ideal;

that is, multiple fan-in branches in a node drive a single line. Figure 1 shows a node that includes fan-in branches, a fan-out

origin, and fan-out branches. Because fan-in and fan-out generally are not ideal in actual circuit layout, the actual topology

of the circuit should be modeled, if it is known, by appropriately adding single-input noninverting buffers to the logic model.

Modeling workarounds may be used to eliminate fan-in to a node. This may be required if the simulator does not directly

model wired connections or bus structures. Some simulators may permit internal fan-in, but require that bidirectional pins to

a DUT be modeled as separate input and output functions.

MIL-STD-883F

METHOD 5012.1

27 July 1990

3.1.3 G-logic and B-logic partitions. Simple components of the logic model (logic primitives such as AND, OR, NAND,

NOR, XOR, buffers, or flip-flops; generally the indivisible primitives understood by a simulator) are herein referred to as gate

logic (G-logic). Complex components of the logic model (such as RAM, ROM, or PLA primitive components, and behavioral

models - relatively complex functions that are treated as "black boxes" for the purpose of fault simulation) are referred to

herein as block logic (B-logic).

For the purpose of fault simulation, the logic model shall be divided into nonoverlapping logic partitions; however, the entire

logic model may consist of a single logic partition. The logic partitions contain components and their associated lines;

although lines may span partitions, no component is contained in more than one partition. A G-logic partition contains only

G-logic; any other logic partition is a B-logic partition.

A logic partition consisting of G-logic, or B-logic, or G-logic and B-logic that, as a unit, is testable using an established testing

algorithm, with known fault coverage or test effectiveness, may be treated as a single B-logic partition.

3.1.4 Model hierarchy

. The logic model may be hierarchical (that is, consisting of macro building blocks), or flat (that is, a

single level of hierarchy with no macro building blocks). Hierarchy does not impose structures on lines; for example, there is

no implied fan-out origin at a macro input or output. Macros that correspond to physical partitions in a model shall use

additional buffers (or an equivalent method) to enforce adherence to the actual DUT's fan-out.

3.1.5 Fractions of transistors

. The fraction of transistors comprising each G-logic and B-logic partition, with respect to the

total count of transistors in the DUT, shall be determined or closely estimated; the total sum of the transistor fractions shall

equal 1. Where the actual transistor counts are not available, estimates may be made on the basis of gate counts or

microcircuit area; the assumptions and calculations supporting such estimates shall be documented in the fault simulation

report. The transistor fractions shall be used in order to weight the fault coverage measured for each individual logic

partition (see 3.5).

3.2 Fault model

3.2.1 G-logic

. The fault model for G-logic shall be permanent stuck-at-zero and stuck-at-one faults on logic lines. Only

single stuck-at faults are considered in calculating fault coverage.

3.2.2 B-logic

. No explicit fault model is assumed for B-logic components. However, an established test algorithm shall

be applied to each B-logic component or logic partition. If a B-logic partition contains logic lines or G-logic components, or

both, justification shall be provided in the fault simulation report as to how the established test algorithm that is applied to the

B-logic partition detects faults associated with the logic lines and G-logic components.

3.2.2.1 Built-in self-test

. A special case of B-logic is a partition that includes a linear-feedback shift register (LFSR) that

performs signature analysis for compression of output error data. Table I lists penalty values for different LFSR degrees. If

the LFSR implements a primitive GF(2) polynomial of degree "k", where there is at least one flip-flop stage between inputs to

a multiple-input LFSR, then the following procedure shall be used in order to determine a lower bound on the established

fault coverage of the logic partition:

Step 1: Excluding the LFSR, but including any stimulus generation logic considered to be part of the logic partition,

determine the fault coverage of the logic partition by fault simulation without signature analysis; denote this fault

coverage by C.

Step 2: Reference table I. For a given degree "k" obtain the penalty value "p". The established fault coverage of the

logic partition using a LFSR of degree "k" shall be reported as (1-p)C. That is, a penalty of (100p) percent is incurred

in assessing the effectiveness of signature analysis if the actual effectiveness is not determined.