MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第700页

MIL-STD-883F METHOD 5012.1 27 July 199 0 6 3.4 Fault simulat ion . 3.4.1 Automat ic t est equipme nt limi tations . Fault c overage repo rted f or the l ogic model of a DUT shall refl ect the limi tations of the tar get …

MIL-STD-883F

METHOD 5012.1

27 July 1990

3.3 Fault universe selection and fault equivalence classing

. Fault coverage shall be reported in terms of equivalence

classes of the detectable faults. This section describes the selection of the initial fault universe, the partitioning or collapsing

of the initial fault universe into fault equivalence classes, and the removal of undetectable faults in order to form the

detectable fault universe. These three stages constitute the fault simulation reporting requirements; however, it is generally

more efficient to obtain the set of faults that represent the fault equivalence classes directly without explicitly generating the

initial fault universe.

3.3.1 Initial fault universe

. The initial fault universe shall consist of single, permanent, stuck-at-zero and stuck-at-one

faults on every logic line (not simply on every logic node) in the G-logic partitions of the logic model. A bus, which is a node

with multiple driving lines, shall be considered, for the purpose of fault universe generation, to be a multiple-input,

single-output logic gate. The initial fault universe shall include stuck-at-zero and stuck-at-one faults on each fan-in and

fan-out branch and the fan-out origin of the bus (see figure 1).

The fault universe does not explicitly contain any faults within B-logic partitions. However, all faults associated with inputs

and outputs of B-logic components either are contained in a G-logic partition or shall be shown to be considered by

established test algorithms that are applied to the B-logic partitions.

No faults shall be added or removed by considering or not considering logic model hierarchy. No extra faults shall be

associated with any primary input or output line, macro input or output line, or logic line that spans logic partitions where the

logic partitions do not correspond to a physical boundary. No more than one stuck-at-zero and one stuck-at-one fault per

logic line shall be contained in the initial fault universe.

3.3.2 Fault equivalence classes

. The initial fault universe shall be partitioned or collapsed into fault equivalence classes

for reporting purposes. The fault equivalence classes shall be chosen such that all faults in a fault equivalence class cause

apparently identical erroneous behavior with respect to the observable outputs of the logic model. One fault from each fault

equivalence class shall be selected to represent the fault class for reporting purposes; these faults shall be called the

representative faults.

For the purpose of implementing this test procedure it is sufficient to apply simple rules to identify structurally-dependent

equivalence classes. An acceptable method for selecting the representative faults for the initial fault universe consists of

listing all single, permanent, stuck-at faults as specified in table II. Any other fault equivalencing procedure used shall be

documented in the fault simulation report. If a bus node exhibits wired-AND or wired-OR behavior in the applicable circuit

technology, then faults associated with that bus shall be collapsed in accordance with the AND or OR fault equivalencing

rules, respectively. Otherwise, no collapsing of faults associated with a bus shall be performed.

3.3.3 Detectable fault universe

. Fault coverage shall be based on the detectable fault universe. Undetectable faults shall

be permitted to be dropped from the set of representative faults; the remaining set of representative faults comprises the

detectable fault universe. In order for a fault to be declared as undetectable, documentation shall be provided in the fault

simulation report as to why there does not exist any test vector sequence capable of guaranteeing that the fault will cause

an error at an observable primary output (see 1.1m.). Any fault not documented in the fault simulation report as being

undetectable shall be considered detectable for the purpose of calculating fault coverage.

MIL-STD-883F

METHOD 5012.1

27 July 1990

3.4 Fault simulation.

3.4.1 Automatic test equipment limitations

. Fault coverage reported for the logic model of a DUT shall reflect the

limitations of the target ATE. Two common cases are:

a. Fault detection during fault simulation shall occur only at times where the ATE will be capable of sensing the

primary outputs of the DUT; there must be a one-to-one correspondence between simulator compares and ATE

compares. For example, if fault coverage for a test vector sequence is obtained using broadside fault simulation

(where fault detection occurs after every change of input stimuli, including clock signals), then it is not correct to

claim the same fault coverage on the ATE if the test vectors are reformatted into cycles where a clock signal is

pulsed during each cycle and compares occur only at the end of each cycle.

b. If the ATE cannot sense the Z output state (either directly or by multiple passes), then the reported fault coverage

shall not include detections involving the Z state. That is, an output value of Z shall be considered to be

equivalent to an output value of X.

Any differences in format or timing of the test vector sequence, between that used by the fault simulator and that

applied by the ATE, shall be documented in the fault simulation report and it shall be shown that fault coverage

achieved on the ATE is not lower than the reported fault coverage.

3.4.2 G-logic

3.4.2.1 Hard detections and potential detections

. Fault coverage for G-logic shall include only faults detected by hard

detections. Potential detections shall not be considered directly in calculating the fault coverage. No number of potential

detections of a fault shall imply that the fault would be detected.

Some potential detections can be converted into hard detections for the purpose of calculating fault coverage. If it can be

shown that a fault is only potentially detected by fault simulation but is in fact detectable by the ATE by a difference not

involving an X value, then upon documenting those conditions in the fault simulation report that fault shall be considered to

be detected as a hard detection and the fault coverage shall be adjusted accordingly.

Faults associated with three-state buffer enable signal lines can cause X states to occur on nodes with fan-in branches, or

erroneous Z states to occur on three-state primary outputs that may be untestable on some ATE. These faults may then be

detectable only as potential detections, but may be unconvertible into hard detections. In such cases, it is permissible for

the fault simulation report to state separately the fraction of the undetected faults that are due to such faults.

3.4.2.2 Fault simulation procedures

. The preferred method of fault simulation for G-logic is to simulate the effect of each

representative fault in the G-logic. However, this may not be practical in some cases due to the large number of

representative faults, or because of limitations of the logic models or simulation tools. In such cases fault sampling

procedures may be used. When fault sampling is used, either the acquisition document shall specify the method of

obtaining a random sample of faults or the fault simulation report shall describe the method used. In either case, the

complete random sample of faults shall be obtained before beginning the fault simulation procedure involving a random

sample of faults.

Use of any fault simulation procedure other than fault simulation procedure 1 (see 3.4.2.2.1) shall be documented and

justified in the fault simulation report.

In this section, it is assumed that the representative faults declared to be undetectable have been removed from the set of

faults to be simulated.

MIL-STD-883F

METHOD 5012.1

27 July 1990

3.4.2.2.1 Fault simulation procedure 1

. Simulate each representative fault in a G-logic partition. The procedure used

shall be equivalent to the following:

Step 1: Denote by "n" the total number of representative faults in the G-logic partition.

Step 2: Fault simulate each representative fault. Denote by "d" the number of hard detections.

Step 3: Fault coverage for the G-logic partition is given by d/n.

3.4.2.2.2 Fault simulation procedure 2

. Obtain lower bound on actual fault coverage in a G-logic partition using fixed

sample size (see table III). The procedure used shall be equivalent to the following:

Step 1: Select a value for the penalty parameter "r" (r = 0.01 to 0.05). The corresponding value of "n" in table III is the

size of the random sample of representative faults.

Step 2: Fault simulate each of the "n" representative faults. Denote by "d" the number of hard detections.

Step 3: The lower bound on the fault coverage is given by "d/n-r".

3.4.2.2.3 Fault simulation procedure 3

. Accept/reject lower bound on fault coverage in a G-logic partition using fixed

sample size (see table IV). The procedure used shall be equivalent to the following:

Step 1: Denote by "F" the minimum required value for fault coverage. From table IV obtain the minimum required

sample size, denoted by "n".

Step 2: Fault-simulate each of the "n" representative faults, and denote by "d" the number of hard detections.

Step 3: If "d" is less than "n" (that is, any faults are undetected), then conclude that the fault coverage is less than "F."

Otherwise (that is, all sampled faults are detected), conclude that the fault coverage is greater than or equal to "F".

3.4.3 B-logic

. Fault coverage shall be measured indirectly for each B-logic partition. For a given B-logic partition, the

established fault coverage or test effectiveness shall be reported for that B-logic partition only if it is shown that: (a) the test

vector sequence applied to the DUT applies the established test algorithm to the B-logic partition, and (b) the resulting

critical output values from the B-logic partition are made observable at the primary outputs. Otherwise, the fault coverage

for that B-logic partition shall be reported as 0 percent. For each B-logic partition tested in this way, the established test

algorithm, proof of its successful application, and the established fault coverage or test effectiveness shall be documented in

the fault simulation report.

3.5 Fault coverage calculation

. Let "m" denote the number of logic partitions in the logic model for the DUT. For the i

logic partition, let "F

" denote its fault coverage (measured in accordance with 3.4), and let "T

" denote its transistor fraction

(measured in accordance with 3.1.5). The fault coverage "F" for the logic model for the DUT shall be calculated as:

F =

+ ... +

12 22 mm

If fault simulation procedure 1 is performed for each G-logic partition in the logic model of a DUT, then the fault coverage for

the logic model of a DUT shall be reported as:

"F of all detectable equivalence classes of single, permanent, stuck-at-zero and stuck-at-one faults on the logic lines of

the logic model as measured by MIL-STD- 883, test method 5012."