MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第701页

MIL-STD-883F METHOD 5012.1 27 July 199 0 7 3.4.2. 2.1 Fault s imulat ion proc edure 1 . Simul ate each r epresen tati ve fault in a G-logi c parti tion. The procedure us ed shall be equival ent to the f ollowi ng: Step 1…

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MIL-STD-883F
METHOD 5012.1
27 July 1990
6
3.4 Fault simulation.
3.4.1 Automatic test equipment limitations
. Fault coverage reported for the logic model of a DUT shall reflect the
limitations of the target ATE. Two common cases are:
a. Fault detection during fault simulation shall occur only at times where the ATE will be capable of sensing the
primary outputs of the DUT; there must be a one-to-one correspondence between simulator compares and ATE
compares. For example, if fault coverage for a test vector sequence is obtained using broadside fault simulation
(where fault detection occurs after every change of input stimuli, including clock signals), then it is not correct to
claim the same fault coverage on the ATE if the test vectors are reformatted into cycles where a clock signal is
pulsed during each cycle and compares occur only at the end of each cycle.
b. If the ATE cannot sense the Z output state (either directly or by multiple passes), then the reported fault coverage
shall not include detections involving the Z state. That is, an output value of Z shall be considered to be
equivalent to an output value of X.
Any differences in format or timing of the test vector sequence, between that used by the fault simulator and that
applied by the ATE, shall be documented in the fault simulation report and it shall be shown that fault coverage
achieved on the ATE is not lower than the reported fault coverage.
3.4.2 G-logic
.
3.4.2.1 Hard detections and potential detections
. Fault coverage for G-logic shall include only faults detected by hard
detections. Potential detections shall not be considered directly in calculating the fault coverage. No number of potential
detections of a fault shall imply that the fault would be detected.
Some potential detections can be converted into hard detections for the purpose of calculating fault coverage. If it can be
shown that a fault is only potentially detected by fault simulation but is in fact detectable by the ATE by a difference not
involving an X value, then upon documenting those conditions in the fault simulation report that fault shall be considered to
be detected as a hard detection and the fault coverage shall be adjusted accordingly.
Faults associated with three-state buffer enable signal lines can cause X states to occur on nodes with fan-in branches, or
erroneous Z states to occur on three-state primary outputs that may be untestable on some ATE. These faults may then be
detectable only as potential detections, but may be unconvertible into hard detections. In such cases, it is permissible for
the fault simulation report to state separately the fraction of the undetected faults that are due to such faults.
3.4.2.2 Fault simulation procedures
. The preferred method of fault simulation for G-logic is to simulate the effect of each
representative fault in the G-logic. However, this may not be practical in some cases due to the large number of
representative faults, or because of limitations of the logic models or simulation tools. In such cases fault sampling
procedures may be used. When fault sampling is used, either the acquisition document shall specify the method of
obtaining a random sample of faults or the fault simulation report shall describe the method used. In either case, the
complete random sample of faults shall be obtained before beginning the fault simulation procedure involving a random
sample of faults.
Use of any fault simulation procedure other than fault simulation procedure 1 (see 3.4.2.2.1) shall be documented and
justified in the fault simulation report.
In this section, it is assumed that the representative faults declared to be undetectable have been removed from the set of
faults to be simulated.
MIL-STD-883F
METHOD 5012.1
27 July 1990
7
3.4.2.2.1 Fault simulation procedure 1
. Simulate each representative fault in a G-logic partition. The procedure used
shall be equivalent to the following:
Step 1: Denote by "n" the total number of representative faults in the G-logic partition.
Step 2: Fault simulate each representative fault. Denote by "d" the number of hard detections.
Step 3: Fault coverage for the G-logic partition is given by d/n.
3.4.2.2.2 Fault simulation procedure 2
. Obtain lower bound on actual fault coverage in a G-logic partition using fixed
sample size (see table III). The procedure used shall be equivalent to the following:
Step 1: Select a value for the penalty parameter "r" (r = 0.01 to 0.05). The corresponding value of "n" in table III is the
size of the random sample of representative faults.
Step 2: Fault simulate each of the "n" representative faults. Denote by "d" the number of hard detections.
Step 3: The lower bound on the fault coverage is given by "d/n-r".
3.4.2.2.3 Fault simulation procedure 3
. Accept/reject lower bound on fault coverage in a G-logic partition using fixed
sample size (see table IV). The procedure used shall be equivalent to the following:
Step 1: Denote by "F" the minimum required value for fault coverage. From table IV obtain the minimum required
sample size, denoted by "n".
Step 2: Fault-simulate each of the "n" representative faults, and denote by "d" the number of hard detections.
Step 3: If "d" is less than "n" (that is, any faults are undetected), then conclude that the fault coverage is less than "F."
Otherwise (that is, all sampled faults are detected), conclude that the fault coverage is greater than or equal to "F".
3.4.3 B-logic
. Fault coverage shall be measured indirectly for each B-logic partition. For a given B-logic partition, the
established fault coverage or test effectiveness shall be reported for that B-logic partition only if it is shown that: (a) the test
vector sequence applied to the DUT applies the established test algorithm to the B-logic partition, and (b) the resulting
critical output values from the B-logic partition are made observable at the primary outputs. Otherwise, the fault coverage
for that B-logic partition shall be reported as 0 percent. For each B-logic partition tested in this way, the established test
algorithm, proof of its successful application, and the established fault coverage or test effectiveness shall be documented in
the fault simulation report.
3.5 Fault coverage calculation
. Let "m" denote the number of logic partitions in the logic model for the DUT. For the i
th
logic partition, let "F
i
" denote its fault coverage (measured in accordance with 3.4), and let "T
i
" denote its transistor fraction
(measured in accordance with 3.1.5). The fault coverage "F" for the logic model for the DUT shall be calculated as:
F =
FT
+
FT
+ ... +
FT
12 22 mm
If fault simulation procedure 1 is performed for each G-logic partition in the logic model of a DUT, then the fault coverage for
the logic model of a DUT shall be reported as:
"F of all detectable equivalence classes of single, permanent, stuck-at-zero and stuck-at-one faults on the logic lines of
the logic model as measured by MIL-STD- 883, test method 5012."
MIL-STD-883F
METHOD 5012.1
27 July 1990
8
If fault simulation procedure 2 or 3 is performed for any G-logic partition, then the fault coverage for the logic model of a DUT
shall be reported as:
"No less than F of all detectable equivalence classes of single, permanent, stuck-at-zero and stuck-at-one faults on the
logic lines of the logic model, with 95 percent confidence, as measured by MIL-STD-883, test method 5012."
The confidence level of 95 percent shall be identified if any fault simulation procedure other than procedure 1 was performed
for any G-logic partition.
4. SUMMARY
. The following details shall be specified in the applicable acquisition document:
a. Minimum required level of fault coverage and method of obtaining fault coverage.
b. If a fault sampling method is permitted, guidance on selection of the random sample of faults.
c. Guidelines, restrictions, or requirements for test algorithms for B-Logic types.
d. The fault simulation report shall provide:
(1) Statement of the overall fault coverage. If there are undetectable faults due to three-state enable signal
lines, then, optionally, fault coverage based on those potential detections may be reported separately.
(2) Description of logic partitions.
(3) Description of test algorithms applied to B-logic. For each B-logic partition tested in this way the established
test algorithm, proof of its successful application, and description of its established fault coverage or test
effectiveness (including classes of faults detected) shall be documented.
(4) Justification for any initial condition, other than X, for any logic line or memory element.
(5) Justification for any approximations used, including estimates of fault coverages, transistor fractions, and
counts of undetectable faults.
(6) Description of any fault equivalencing procedure used in lieu of the procedure defined by table II.
(7) Justification for declaring any fault to be undetectable.
(8) In the event that the test vector sequence is formatted differently between the ATE and the fault simulator,
justification that fault coverage achieved on the ATE is not lower than the reported fault coverage.
(9) Justification of the use of fault simulation procedure 2 or 3 rather than fault simulation procedure 1.
(10) When fault sampling is used, description of the method of obtaining a random sample of faults.
(11) In the event that the fault simulation procedure used is not obviously equivalent to fault simulation procedure
1, 2, or 3, justification as to why it yields equivalent results.
(12) In the event that a test technique or design-for-testability approach is used that provides additional control or
observation test points beyond those provided by the DUT's primary inputs and primary outputs (see 1.1j),
justification that the stated fault coverage is valid.
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