MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS - 第702页

MIL-STD-883F METHOD 5012.1 27 July 199 0 8 If f ault simul ation pr ocedure 2 or 3 is per form ed for any G-l ogic par titi on, then t he fault coverage f or the l ogic model of a D UT shall be report ed as: "No les…

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MIL-STD-883F
METHOD 5012.1
27 July 1990
7
3.4.2.2.1 Fault simulation procedure 1
. Simulate each representative fault in a G-logic partition. The procedure used
shall be equivalent to the following:
Step 1: Denote by "n" the total number of representative faults in the G-logic partition.
Step 2: Fault simulate each representative fault. Denote by "d" the number of hard detections.
Step 3: Fault coverage for the G-logic partition is given by d/n.
3.4.2.2.2 Fault simulation procedure 2
. Obtain lower bound on actual fault coverage in a G-logic partition using fixed
sample size (see table III). The procedure used shall be equivalent to the following:
Step 1: Select a value for the penalty parameter "r" (r = 0.01 to 0.05). The corresponding value of "n" in table III is the
size of the random sample of representative faults.
Step 2: Fault simulate each of the "n" representative faults. Denote by "d" the number of hard detections.
Step 3: The lower bound on the fault coverage is given by "d/n-r".
3.4.2.2.3 Fault simulation procedure 3
. Accept/reject lower bound on fault coverage in a G-logic partition using fixed
sample size (see table IV). The procedure used shall be equivalent to the following:
Step 1: Denote by "F" the minimum required value for fault coverage. From table IV obtain the minimum required
sample size, denoted by "n".
Step 2: Fault-simulate each of the "n" representative faults, and denote by "d" the number of hard detections.
Step 3: If "d" is less than "n" (that is, any faults are undetected), then conclude that the fault coverage is less than "F."
Otherwise (that is, all sampled faults are detected), conclude that the fault coverage is greater than or equal to "F".
3.4.3 B-logic
. Fault coverage shall be measured indirectly for each B-logic partition. For a given B-logic partition, the
established fault coverage or test effectiveness shall be reported for that B-logic partition only if it is shown that: (a) the test
vector sequence applied to the DUT applies the established test algorithm to the B-logic partition, and (b) the resulting
critical output values from the B-logic partition are made observable at the primary outputs. Otherwise, the fault coverage
for that B-logic partition shall be reported as 0 percent. For each B-logic partition tested in this way, the established test
algorithm, proof of its successful application, and the established fault coverage or test effectiveness shall be documented in
the fault simulation report.
3.5 Fault coverage calculation
. Let "m" denote the number of logic partitions in the logic model for the DUT. For the i
th
logic partition, let "F
i
" denote its fault coverage (measured in accordance with 3.4), and let "T
i
" denote its transistor fraction
(measured in accordance with 3.1.5). The fault coverage "F" for the logic model for the DUT shall be calculated as:
F =
FT
+
FT
+ ... +
FT
12 22 mm
If fault simulation procedure 1 is performed for each G-logic partition in the logic model of a DUT, then the fault coverage for
the logic model of a DUT shall be reported as:
"F of all detectable equivalence classes of single, permanent, stuck-at-zero and stuck-at-one faults on the logic lines of
the logic model as measured by MIL-STD- 883, test method 5012."
MIL-STD-883F
METHOD 5012.1
27 July 1990
8
If fault simulation procedure 2 or 3 is performed for any G-logic partition, then the fault coverage for the logic model of a DUT
shall be reported as:
"No less than F of all detectable equivalence classes of single, permanent, stuck-at-zero and stuck-at-one faults on the
logic lines of the logic model, with 95 percent confidence, as measured by MIL-STD-883, test method 5012."
The confidence level of 95 percent shall be identified if any fault simulation procedure other than procedure 1 was performed
for any G-logic partition.
4. SUMMARY
. The following details shall be specified in the applicable acquisition document:
a. Minimum required level of fault coverage and method of obtaining fault coverage.
b. If a fault sampling method is permitted, guidance on selection of the random sample of faults.
c. Guidelines, restrictions, or requirements for test algorithms for B-Logic types.
d. The fault simulation report shall provide:
(1) Statement of the overall fault coverage. If there are undetectable faults due to three-state enable signal
lines, then, optionally, fault coverage based on those potential detections may be reported separately.
(2) Description of logic partitions.
(3) Description of test algorithms applied to B-logic. For each B-logic partition tested in this way the established
test algorithm, proof of its successful application, and description of its established fault coverage or test
effectiveness (including classes of faults detected) shall be documented.
(4) Justification for any initial condition, other than X, for any logic line or memory element.
(5) Justification for any approximations used, including estimates of fault coverages, transistor fractions, and
counts of undetectable faults.
(6) Description of any fault equivalencing procedure used in lieu of the procedure defined by table II.
(7) Justification for declaring any fault to be undetectable.
(8) In the event that the test vector sequence is formatted differently between the ATE and the fault simulator,
justification that fault coverage achieved on the ATE is not lower than the reported fault coverage.
(9) Justification of the use of fault simulation procedure 2 or 3 rather than fault simulation procedure 1.
(10) When fault sampling is used, description of the method of obtaining a random sample of faults.
(11) In the event that the fault simulation procedure used is not obviously equivalent to fault simulation procedure
1, 2, or 3, justification as to why it yields equivalent results.
(12) In the event that a test technique or design-for-testability approach is used that provides additional control or
observation test points beyond those provided by the DUT's primary inputs and primary outputs (see 1.1j),
justification that the stated fault coverage is valid.
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MIL-STD-883F
METHOD 5012.1
27 July 1990
9
FIGURE 1. Node consisting of fan-in branches, a fan-out origin, and fan-out branches
.
TABLE I. Penalty values, P, for LFSR signature analyzers implementing primitive polynomial of degree k
.
K
p
k < 8
k = (8...15)
k = (16...23)
k > 23
1.0
0.05
0.01
0.0
TABLE II. Representative faults for the fault equivalence classes
.
Stuck-at faults
Type of logic line in logic model
s-a-1
s-a-0
s-a-0, s-a-1
s-a-0, s-a-1
s-a-0, s-a-1
Every input of multiple-input AND or NAND gates
Every input of multiple-input OR or NOR gates
Every input of multiple-input components
that are not AND, OR, NAND, or NOR gates
Every logic line that is a fan-out origin
Every logic line that is a primary output
Note: "s-a-0" is stuck-at-zero and "s-a-1" is stuck-at-one.