ISM6636A&B_Rev1.10解密.pdf - 第21页
21 Innovision Semiconductor Prelim inary Data sheet ISM6636 A/B Rev1.10 01/2023 Table 6 List of register desc riptions Reg Name Bits Read Write Description ISM6636A Default ISM6636B Default 0x1B I2CEnable [0] R/W [0] = 0…
20
Innovision Semiconductor
Preliminary Datasheet
ISM6636A/B
Rev1.10 01/2023
ISM6636X registers
Register Description
Reg
Name
Bits
Read
Write
Description
ISM6636A
Default
ISM6636B
Default
0x0A
Product_ID
[7:0]
R
Device identification.
0x36
0x36
0x0B
IC_Version
[7:0]
R
Silicon version.
0x01
0x01
0x0C
Pvin_Report
[7:0]
R
PVIN Range: 0->16V
1/16 V resolution.
\
\
0x0D
Vout_Report
[7:0]
R
Range: 0.8V --> 5.7V, 20mV
resolution.
\
\
0x0E
Iout_Report
[7:0]
R
Iout Range: 0A --> 8.2A
40mA Resolution.
\
\
0x0F
Temp_Report
[7:0]
R
Range: -40°C--180°C
1°C resolution.
\
\
0x11
Ramp_Amplitu
de
[3:0]
R/W
Adjust compensation ramp.
[3:0]=0110
[3:0]=0111
0x12
Vout_High_Bit
[0]
R/W
Set Vout voltage.
DAC Range 0.8V-->5.5V by
10mV step.
\
\
0x13
Vout_Low_Byte
[7:0]
R/W
\
\
0x14
Soft Start_Rate
[4:3]
R/W
[4:3]=00 : 1mV/µs;
[4:3]=01 : 2mV/µs;
[4:3]=10 : 0.5mV/µs;
[4:3]=11 : 4mV/µs;
[4:3]=00
[4:3]=00
Soft Stop
Enable
[2]
R/W
[2]=0: Disable; [2]=1: Enable;
[2]=0
[2]=0
FCCM and
DCM
[1]
R/W
If [1]=0 Select FCCM ;
If [1]=1 and EN<2.5V, Select
DCM.
If [1]=1 and EN>2.5V,Select
FCCM.
[1]=1
[1]=1
0x17
OV_Threshold
[1:0]
R/W
[1:0]=00 : 105%;
[1:0]=01 : 110%;
[1:0]=10 : 115%;
[1:0]=11 : 120%;
Default is 120%.
[1:0]=11
[1:0]=11
0x18
PG_Threshold
[1:0]
R/W
[1:0]=00 : 80%;
[1:0]=01 : 85%;
[1:0]=10 : 90%;
[1:0]=11 : 95%;
Default is 90%.
[1:0]=10
[1:0]=10
0x19
OT_Threshold
[1:0]
R/W
[1:0]=00 : 75°C;
[1:0]=01 : 85°C;
[1:0]=10 : 125° C;
[1:0]=11 : 145° C;
Default is 145° C.
[1:0]=11
[1:0]=11
0x1A
OV_Response
[0]
R/W
Behavior after triggering OV.
[0]=0 : Latch off;
[0]=1 : No-Latch off;
[0]=0
[0]=0
21
Innovision Semiconductor
Preliminary Datasheet
ISM6636A/B
Rev1.10 01/2023
Table 6 List of register descriptions
Reg
Name
Bits
Read
Write
Description
ISM6636A
Default
ISM6636B
Default
0x1B
I2CEnable
[0]
R/W
[0] = 0 : Disable I2C Power
on;
[0] =1 : Enable I2C Power
on;
[0]=1
[0]=1
0x1C
Soft Stop
Power down
[3]
R/W
[3] =0 :Power on;
[3] =1 :Soft Stop Power
down;
[3] =0
[3] =0
0x1D
User_OTP_ON
[1]
R/W
Add an option to avoid OTP
malfunction
[1]=1 :EnableOTP function
(turn on OTP clock) .
[1]=0 :DisableOTP function
(turn on OTP clock) .
[1]=0
[1]=0
0x20
User_Pointer
[5:3]
R
Read internal OTP writable
times.
[5:3]=000; OTP can be
written 3 times.
[5:3]=001; OTP can be
written 2 times.
[5:3]=011; OTP can be
written 1 times.
[5:3]=111; OTP can be
written 0 times.
[5:3]=001
[5:3]=001
0x21
Status_PG
[7]
R
Reflects real-time PG status.
\
\
Status_OVP
[6]
R
Read the OVP state.
\
\
Status_OCP
[5]
R
Read the OCP state.
\
\
Status_OTP
[4]
R
Read the OTP state.
\
\
Status_Enable
[3]
R
Reflects real-time Enable
status.
\
\
0x2B
User_OTP_pro
gram
[7:0]
R/W
Write register data to OTP.
\
\
22
Innovision Semiconductor
Preliminary Datasheet
ISM6636A/B
Rev1.10 01/2023
ADC Telemetry Reporting Min/Max Corresponding Binary and
Hexadecimals
MIN
HEX
BIN
TYP
HEX
BIN
MAX
HEX
BIN
PVIN Report
0
0
0000 0000
12V
C0
1100 0000
16V
FF
1111 1111
VOUT Report
0.8V
0A
0000 1010
3.6V
96
1001 0110
5.7V
FF
1111 1111
IOUT Report
0A
32
0011 0010
6A
C8
1100 1000
8.2A
FF
1111 1111
Temp Report
-40°C
23
0010 0011
20°C
60
0110 0000
180°C
FF
1111 1111
Table 7 List of register descriptions
I2C protocol
S = Start bit A = Ack
P = Stop bit Na= Nack
W= “0” （Write bit） Sr = Repeated start
R = “1”（Read bit）
a) Send Command Code
1
7
1
1
8
1
1
S
SLAVE
ADDRESS
W
A
COMMAND
CODE
A
P
b) Write Byte
1
7
1
1
8
1
8
1
1
S
SLAVE
ADDRESS
W
A
REGISTER
CODE
A
DATA BYTE
A
P
c) Read Byte
1
7
1
1
8
1
1
7
1
1
8
1
1
S
SLAVE
ADDRESS
W
A
REGISTER
CODE
A
S
r
SLAVE
ADDRESS
R
A
DATA BYTE
N
A
P
Table8 I2C protocol