ISM6636A&B_Rev1.10解密.pdf - 第8页

8 Innovision Semiconductor Preliminary Datas heet ISM6636 A/B Rev1.10 01/2023 Thermal Shut-Dow n TSD (default) Thermal Shut-Down 145 °C Hysteresis 25 Under-Voltage Lock-Out a nd Enable VCC_UVLO (START) VCC Start Threshol…

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7
Innovision Semiconductor
Preliminary Datasheet
ISM6636A/B
Rev1.10 01/2023
Electrical Characteristics
Unless otherwise stated, specifications apply over: 5V < PVIN = VIN< 16V, 0°C < TA <
125°C,Typical values are specified at TA= 25°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supply Current
I
IN
(STANDBY)
VIN Supply Current
(Standby)
Enable low
1
mA
I
IN
(STATIC)
VIN Supply Current
(Static)
No switching, EN = 2V
2.3
I
IN
(DYN)
VIN Supply Current
(Dynamic)
EN high, VIN = 12V, V
OUT
= 5.0V, F
SW
=
1.875MHz(Note 2)
23
Soft-Start
SS
VOS Soft-Start Rate
Default
1
V/ms
Output Voltage
VOUT
VOUT (default)
5
V
Resolution
10
mV
Accuracy
Tj= 25°C, PVIN = 12V,
VOUT = 5V
±0.5
%
25°C< Tj< 125°C, PVIN =
12V, VOUT= 3.3V
-1
1
25°C< Tj< 125°C, PVIN =
12V, VOUT= 5V
-1.2
1.2
On-Time Timer Control
T
ON
On Time
PVIN = 12V, VOUT = 5V,
FSW = 1.875MHz
222
ns
T
ON
(MIN)
Minimum On-Time
(Note 2)
40
T
OFF
(MIN)
Minimum Off-Time
(Note 2)
184
SW Frequency
Fsw
SW Frequency
PVIN = 12V, VOUT =
3.3V, VOS connect to
VOUT.
1.875
MHz
PVIN = 12V, VOUT =
5.0V, VOS connect to
VOUT.
1.875
Accuracy
-15
+15
%
Internal Low Drop-Out (LDO) Regulator
VCC
LDO Regulator
Output Voltage
5.5V < VIN ≤ 16V, 0 -
20mA
4.8
5
5.2
V
5 ≤ VIN< 5.5V, 0 - 20mA
4.3
VLN
Line Regulation
5.5V < VIN ≤ 16V, 20mA
200
mV
VLD
Load Regulation
VIN = 12V, 0 - 20mA
100
8
Innovision Semiconductor
Preliminary Datasheet
ISM6636A/B
Rev1.10 01/2023
Thermal Shut-Down
TSD (default)
Thermal Shut-Down
145
°C
Hysteresis
25
Under-Voltage Lock-Out and Enable
VCC_UVLO(START)
VCC Start Threshold
VCC Rising Trip Level
3.7
4.0
4.2
V
VCC_UVLO(STOP)
VCC Stop Threshold
VCC Falling Trip Level
3.6
3.8
3.95
En(HIGH)
Enable Threshold
Ramping Up
1.1
1.2
1.3
En(LOW)
Enable Threshold
Ramping Down
0.95
1
1.05
V
REN
Input Impedance
3V < V
EN
< 18V
500
1000
1500
kΩ
Current Limit
IOC
DC IOUT Current
limit
TJ = 25°C, VOUT = 3.3V,
5
5.7
6.4
A
TJ = 25°C, VOUT = 5V,
4.7
5.4
6.1
Val_OC
Valley Current Limit
TJ = 25°C, VOUT = 3.3V
3.8
4.3
4.8
A
TJ = 25°C, VOUT = 5V
3.8
4.3
4.8
TBLK(HICCUP)
Hiccup Blanking
Time
(Note 2)
25
ms
Over-Voltage Protection
VOVP
Output Over-Voltage
Protection Threshold
OVP Detect
OV_Threshold[1:0] = 11
115
120
125
VOS%
TOVPDEL
Output Over-voltage
Protection Delay
(Note 2)
7
µs
Power Good (PG)
VPG(UPPER)(default)
Power Good Upper
Threshold
VOUT Rising
85
90
95
VOS%
VPG(LOWER)
Power Good
Hysteresis
VOUT Falling
5
IPG
Power Good Sink
Current
PG = 0.5V, En = 2V
10
mA
9
Innovision Semiconductor
Preliminary Datasheet
ISM6636A/B
Rev1.10 01/2023
Unless otherwise stated, specifications apply over: 5V < PVIN = VIN< 16V, 0°C < TA <
125°C,Typical values are specified at TA= 25°C
I
2
C PARAMETER
CONDITIONS
(Note 2)
Fast-mode
Fast-mode plus
UNIT
MIN
MAX
MIN
MAX
T
OF
Output fall time
From V
IHmin
to
V
ILmax
20 × (VDD
/ 5.5 V)
250
20 × (VDD
/ 5.5 V)
125
ns
T
SP
Pulse width of spikes
that must be
suppressed by the
input filter
0
50
0
50
I
I
Input current each I/O
pin
PG = 0.5V, En =
2V
-10
10
-10
10
µA
C
I
Capacitance for each
I/O pin
10
10
pF
F
SCL
SCL clock frequency
0
400
0
1000
kHz
T
HD;STA
Hold time (repeated)
START condition
After this period,
the first clock
pulse is generated
0.6
0.26
µs
T
LOW
LOW period of the
SCL clock
1.3
0.5
T
HIGH
HIGH period of the
SCL clock
0.6
0.26
T
SU;STA
Set-up time for a
repeated START
condition
0.6
0.26
T
HD;DAT
Data hold time
I
2
C-bus devices
0
0
T
SU;DAT
Data set-up time
100
50
ns
T
R
Rise time of SDA and
SCL signals
20
300
120
T
F
Fall time of SDA and
SCL signals
20 × (VDD
/ 5.5 V)
300
20 × (VDD
/ 5.5 V)
120
T
SU;STO
Set-up time for STOP
condition
0.6
0.26
µs
T
BUF
Bus free time
between a STOP and
START condition
1.3
0.5
C
B
Capacitive load for
each bus line
400
550
pF
T
VD;DAT
Data valid time
0.9
0.45
µs
T
VD;ACK
Data valid
acknowledge time
0.9
0.45
V
NL
Noise margin at the
LOW level
For each
connected device,
including
hysteresis
0.1VDD
0.1VDD
V
V
NH
Noise margin at the
HIGH level
0.2VDD
0.2VDD
T
TO
SDA timeout
200
200
µs
Note 2. Guaranteed by design but not tested in production.